CVS commit: [netbsd-6] src/sys/arch/x86/include

["Martin Husemann" <martin%netbsd.org@localhost>]

Module Name:    src
Committed By:   martin
Date:           Mon Dec 29 15:14:27 UTC 2014

Modified Files:
        src/sys/arch/x86/include [netbsd-6]: cacheinfo.h

Log Message:
Pullup the following revisions, requested by msaitoh in #1219:

sys/arch/x86/include/cacheinfo.h                1.14-1.19

        Update Intel's cache and TLB descripotr table. This changes the number
        of page coloring on some CPUs.
        - Add Shared L2 TLB.
        - Support prefetch size.
        - Add some new TLB and cache entries from the document.
        - Fix some entries:
          - Fix 0x0d's DCACHE entry and 0xeb's L3CACHE entry.
          - Desc 0x55 and 0xb1 are Instruction TLB but not fixed to 4K.
          - Desc 0x5a and 0xc0 are Data TLB but not fixed to 4K.
          - Desc 0x57 and 0x59 are 4K fixed DTLB.
          - Fix string of desc 0xc2 and it's not fixed to 4K.
          - Desc 0xca is 4K fixed L2 shared TLB.


To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.13.2.1 src/sys/arch/x86/include/cacheinfo.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.