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CVS commit: src/tests/lib/libc/gen
Module Name: src
Committed By: martin
Date: Sun Aug 10 12:01:57 UTC 2014
Do not set HAVE_FENV for arm as long as it misses feenableexcept().
To generate a diff of this commit:
cvs rdiff -u -r1.42 -r1.43 src/tests/lib/libc/gen/Makefile
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
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