Source-Changes archive

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]

CVS commit: [matt-nb5-mips64] src/sys/arch



Module Name:    src
Committed By:   matt
Date:           Wed Jan  4 16:17:55 UTC 2012

Modified Files:
        src/sys/arch/evbmips/conf [matt-nb5-mips64]: XLPEVB
        src/sys/arch/evbmips/rmixl [matt-nb5-mips64]: autoconf.c machdep.c
        src/sys/arch/mips/conf [matt-nb5-mips64]: files.rmixl
        src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_cpu.c rmixl_cpucore.c
            rmixl_cpunode.c rmixl_fmn.c rmixl_fmnvar.h rmixl_gpio_pci.c
            rmixl_intr.c rmixl_intr.h rmixl_pcie.c rmixl_pcix.c rmixlp_pcie.c
            rmixlreg.h rmixlvar.h
Added Files:
        src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_machdep.c
            rmixl_pci_eb_mem_space.c rmixl_pci_el_mem_space.c
Removed Files:
        src/sys/arch/mips/rmi [matt-nb5-mips64]: rmixl_pci_mem_space.c

Log Message:
Rework Fast Messaging Network support (it's now lockless).
Workaround a problem with bus 0 BAR sizing causing the registers behind
the BAR to become inaccessible.
Move much/most of the startup code from evbmips/rmixl/machdep to
mips/rmi/rmixl_machdep.c
Move the code to find the XLP variant to the early boot so it can be used
early.
8bit and 16bit accessed to PCI bus 0 cause cache errors so chagne the access
of pci mem to 32bits.


To generate a diff of this commit:
cvs rdiff -u -r1.1.2.4 -r1.1.2.5 src/sys/arch/evbmips/conf/XLPEVB
cvs rdiff -u -r1.1.2.5 -r1.1.2.6 src/sys/arch/evbmips/rmixl/autoconf.c
cvs rdiff -u -r1.1.2.43 -r1.1.2.44 src/sys/arch/evbmips/rmixl/machdep.c
cvs rdiff -u -r1.1.2.17 -r1.1.2.18 src/sys/arch/mips/conf/files.rmixl
cvs rdiff -u -r1.1.2.22 -r1.1.2.23 src/sys/arch/mips/rmi/rmixl_cpu.c
cvs rdiff -u -r1.1.2.12 -r1.1.2.13 src/sys/arch/mips/rmi/rmixl_cpucore.c
cvs rdiff -u -r1.1.2.5 -r1.1.2.6 src/sys/arch/mips/rmi/rmixl_cpunode.c \
    src/sys/arch/mips/rmi/rmixl_fmnvar.h
cvs rdiff -u -r1.1.2.8 -r1.1.2.9 src/sys/arch/mips/rmi/rmixl_fmn.c
cvs rdiff -u -r1.1.2.4 -r1.1.2.5 src/sys/arch/mips/rmi/rmixl_gpio_pci.c
cvs rdiff -u -r1.1.2.33 -r1.1.2.34 src/sys/arch/mips/rmi/rmixl_intr.c
cvs rdiff -u -r1.1.2.11 -r1.1.2.12 src/sys/arch/mips/rmi/rmixl_intr.h \
    src/sys/arch/mips/rmi/rmixl_pcix.c
cvs rdiff -u -r0 -r1.1.2.1 src/sys/arch/mips/rmi/rmixl_machdep.c \
    src/sys/arch/mips/rmi/rmixl_pci_eb_mem_space.c \
    src/sys/arch/mips/rmi/rmixl_pci_el_mem_space.c
cvs rdiff -u -r1.1.2.2 -r0 src/sys/arch/mips/rmi/rmixl_pci_mem_space.c
cvs rdiff -u -r1.1.2.20 -r1.1.2.21 src/sys/arch/mips/rmi/rmixl_pcie.c
cvs rdiff -u -r1.1.2.6 -r1.1.2.7 src/sys/arch/mips/rmi/rmixlp_pcie.c
cvs rdiff -u -r1.1.2.18 -r1.1.2.19 src/sys/arch/mips/rmi/rmixlreg.h
cvs rdiff -u -r1.1.2.24 -r1.1.2.25 src/sys/arch/mips/rmi/rmixlvar.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




Home | Main Index | Thread Index | Old Index