CVS commit: src/sys/arch/mips/mips

["Izumi Tsutsui" <tsutsui%netbsd.org@localhost>]

Module Name:    src
Committed By:   tsutsui
Date:           Tue Mar  8 15:12:46 UTC 2011

Modified Files:
        src/sys/arch/mips/mips: locore_mips1.S

Log Message:
Pass correct exception PC value to cpu_intr() as mipsX_subr.S does.
Fixes SIGILL on all FPU exceptions on R3000.

XXX: cpu_intr() may require cause value as mentioned in PR port-mips/44639


To generate a diff of this commit:
cvs rdiff -u -r1.74 -r1.75 src/sys/arch/mips/mips/locore_mips1.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.