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CVS commit: src/sys/arch/mips/mips



Module Name:    src
Committed By:   tsutsui
Date:           Sat Feb 26 13:58:35 UTC 2011

Modified Files:
        src/sys/arch/mips/mips: locore.S

Log Message:
- clear MIPS_FPU_EXCEPTION_BITS in MIPS_FPU_CSR in SIGILL case
  as noted in commit log of rev 1.158
- update comment to reflect changes in rev 1.109


To generate a diff of this commit:
cvs rdiff -u -r1.182 -r1.183 src/sys/arch/mips/mips/locore.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.



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