Module Name:	src
Committed By:	dyoung
Date:		Fri Nov 16 18:36:53 UTC 2007

Modified Files:
	src/sys/dev/cardbus: cardbus.c cardbusvar.h
	src/sys/dev/pci: pccbb.c pccbbreg.h

Log Message:
Improve Cardbus performance, error handling, and error reporting.

Let the TI1420 PCI-Cardbus bridge do burst reads from the primary
(PCI) bus.  This ought to improve Tx performance on Cardbus NICs.
This optimization may apply to other TI bridges, but I only have
a datasheet for the TI1420. :-/

Activate PCI Parity Error and System Error reporting on PCI-Cardbus
bridges.

To avoid data destruction, set the Master Abort mode to 1.  Stops
the bridge from silently discarding writes from the secondary bus
to the primary bus (Cardbus writes to PCI).  Also, stops the bridge
from fulfilling a read by a bus master on the secondary bus that
failed on the primary bus with 0xffffffff (Cardbus reads from PCI).
Now the bus will indicate an error condition (SERR) instead of
silently destroying/corrupting data.

Forward system error indications from the secondary to the primary
bus.  Detect parity errors on the secondary.

Set a Cardbus card's Latency Timer to something reasonable, according
to the Cardbus card's Minimum Grant and the bandwidth available on
the PCI bus.  Restore the Latency Timer when re-enabling a card
(e.g., after power reactivation).


To generate a diff of this commit:
cvs rdiff -r1.76 -r1.77 src/sys/dev/cardbus/cardbus.c
cvs rdiff -r1.35 -r1.36 src/sys/dev/cardbus/cardbusvar.h
cvs rdiff -r1.150 -r1.151 src/sys/dev/pci/pccbb.c
cvs rdiff -r1.12 -r1.13 src/sys/dev/pci/pccbbreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.