On Nov 12, 2006, at 12:20 PM, David Laight wrote:

> Dunno, but there are a few DSPs out there with ethernet interfaces
> that require aligned RX buffers, but where the (big-endian) cpu can't
> read misaligned data.  The h/w guys want shooting, 2 bytes of any- 
> value
> would do...

On chips that can do it, another possible approach is to set up your  
buffer like this:

[ethernet header][2 byte pad][rest of packet]

..and use two descriptors per packet, one for the header, one for the  
remainder of the packet, and then  memmove() the Ethernet header  
forward 2 bytes after receiving the packet.

This gets tricky with Jumbo-capable interfaces, however, because you  
potentially need multiple descriptors for the payload, and thus don't  
know where the header will wind up.

-- thorpej