On Fri, Oct 20, 2006 at 03:44:00PM +0000, Izumi Tsutsui wrote:
> 
> Module Name:	src
> Committed By:	tsutsui
> Date:		Fri Oct 20 15:44:00 UTC 2006
> 
> Modified Files:
> 	src/sys/dev/ic: rtl8169.c
> 
> Log Message:
> Use BUS_DMA_COHERENT on mapping DMA memory for TX/RX descriptors.

BUS_DMA_COHERENT is advice for the bus_dma backend.  The backend may
ignore it.  Quoting bus_dma(9),

                     BUS_DMA_COHERENT  This flag is a hint to machine-depen-
                                       dent code.  If possible, map the memory
                                       in such a way as it will be DMA coher-
                                       ent.  This may include mapping the
                                       pages into uncached address space or
                                       setting the cache-inhibit bits in page
                                       table entries.  If DMA coherent map-
                                       pings are impossible, this flag is
                                       silently ignored.

> I can't think of a good way to avoid race condition between writeback and
> DMA write against descriptors if cachelinesize > sizeof(struct rtk_desc)...

You must pad struct rtk_desc to the cacheline size to avoid cacheline
interference.  I cannot emphasize enough how important that is!

bus_dma really ought to provide a #define for the machine's cacheline
size.

Dave

> Anyway, now re(4) is functional on O2 (and probably other mips ports).
> 
> 
> To generate a diff of this commit:
> cvs rdiff -r1.38 -r1.39 src/sys/dev/ic/rtl8169.c
> 
> Please note that diffs are not public domain; they are subject to the
> copyright notices on the relevant files.

-- 
David Young             OJC Technologies
dyoung@ojctech.com      Urbana, IL * (217) 278-3933