Module Name:	src
Committed By:	briggs
Date:		Thu May 19 20:11:24 UTC 2005

Modified Files:
	src/sys/dev/ic: rtl8169.c

Log Message:
BUS_DMASYNC_* routines are from the point of view of the memory controller,
so BUS_DMASYNC_POSTREAD should follow a device->memory transfer (like for
the rx packet data.
Also, it would be good to do a BUS_DMASYNC_PREWRITE to ensure that packet
data is flushed to memory before the chip tries to transmit data.
Tested on a PowerPC system.


To generate a diff of this commit:
cvs rdiff -r1.19 -r1.20 src/sys/dev/ic/rtl8169.c

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