Module Name:	src
Committed By:	pk
Date:		Tue Apr 27 13:05:38 UTC 2004

Modified Files:
	src/sys/arch/sparc/include: ctlreg.h

Log Message:
Bits 0 (MMU Enable) and 1 (Fault inhibit) are common among the implementations
of the SRMMU control register. Reflect that fact in the definitions here.

Also add the swift `store allocate' bit.


To generate a diff of this commit:
cvs rdiff -r1.25 -r1.26 src/sys/arch/sparc/include/ctlreg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.