> > Using:
> > 
> > 	__asm __volatile("":::"memory");
> > 
> > on both sides of the RAS ought to be enough, if the RAS doesn't operate 
> > on any locals.
> 
> Thanks, I'll try that and remove the -O0 if it works.
> 
> Should we turn that into a macro to stay gcc-neutral?

You might also consider this:

	#define __insn_barrier()        __asm __volatile("": : : "g0")

(see sparc/include/cdefs.h), which prevents instruction re-ordering
but does not include the `memory clobber' that will cause register
reloads on the other side.

-pk