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CVS commit: src/sys/arch/powerpc/powerpc



Module Name:    src
Committed By:   matt
Date:           Wed Oct 22 17:27:58 UTC 2003

Modified Files:
        src/sys/arch/powerpc/powerpc: trap_subr.S

Log Message:
Rework ddblow so that if PSL_PR == 1, it dispatches directly to the
trap handler and bypasses the ddbtrap code.


To generate a diff of this commit:
cvs rdiff -r1.50 -r1.51 src/sys/arch/powerpc/powerpc/trap_subr.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




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