Module Name:	basesrc
Committed By:	simonb
Date:		Tue Dec 17 12:10:04 UTC 2002

Modified Files:
	basesrc/doc: CHANGES

Log Message:
Note support of fully coherent data caches for MIPS32/64 CPUs.


To generate a diff of this commit:
cvs rdiff -r1.55 -r1.56 basesrc/doc/CHANGES

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.