Module Name:	syssrc
Committed By:	thorpej
Date:		Wed Aug 14 22:56:56 UTC 2002

Modified Files:
	syssrc/sys/arch/arm/arm32: bus_dma.c

Log Message:
When doing PREREAD sync operations, if the start and end addresses
of the range are aligned to a cacheline boundary, when do a dcache-inv
operation, rather than a dcache-wbinv operation.

XXX It could be a little smarter (align using wbinv, inv, then finish
up using wbinv), but even this simple change is good for a nearly 40%
improvement in my test case on XScale.


To generate a diff of this commit:
cvs rdiff -r1.17 -r1.18 syssrc/sys/arch/arm/arm32/bus_dma.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.