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CVS commit: syssrc/sys/arch/arm/arm
Module Name: syssrc
Committed By: thorpej
Date: Wed Aug 14 22:53:20 UTC 2002
Modified Files:
syssrc/sys/arch/arm/arm: cpufunc_asm_xscale.S
Log Message:
Fix a fencepost in the cache flush routines, caused by using the wrong
condition on a branch (bpl where bhi should have been used). The error
caused one more line than intended to be flushed, which is particularly
bad if you're doing a dcache-invalidate operation.
To generate a diff of this commit:
cvs rdiff -r1.14 -r1.15 syssrc/sys/arch/arm/arm/cpufunc_asm_xscale.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
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