Module Name:	syssrc
Committed By:	wdk
Date:		Sat Dec 15 11:11:49 UTC 2001

Modified Files:
	syssrc/sys/arch/mipsco/obio: asc.c

Log Message:
Add bus_dmamap_sync for pre-read and pre-write case.   This was previously
left out as it was a no-op on the R3000 processor.  However, recent changes
to the Mips cache ops highlighted we should DTRT in case the MI/MD layer
choses to invalidate the cache ahead of the DMA instead of after it.


To generate a diff of this commit:
cvs rdiff -r1.9 -r1.10 syssrc/sys/arch/mipsco/obio/asc.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.