source-changes: CVS commit: [thorpej-mips-cache] syssrc/sys/arch/mips/mips

Subject: CVS commit: [thorpej-mips-cache] syssrc/sys/arch/mips/mips
To: None <source-changes@netbsd.org>
From: Jason R Thorpe <thorpej@netbsd.org>
List: source-changes
Date: 11/14/2001 18:45:07

Module Name:	syssrc
Committed By:	thorpej
Date:		Wed Nov 14 16:45:07 UTC 2001

Modified Files:
	syssrc/sys/arch/mips/mips [thorpej-mips-cache]: cache_r5k.c

Log Message:
Be more conservative with interrupt blocking in the R4600 ops
that require chip bug work-arounds.

XXX Should probably just consider using Index ops where feasible on
the buggy R4600s.


To generate a diff of this commit:
cvs rdiff -r1.1.2.3 -r1.1.2.4 syssrc/sys/arch/mips/mips/cache_r5k.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.