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CVS commit: syssrc/sys/arch/arm/xscale



Module Name:    syssrc
Committed By:   thorpej
Date:           Fri Nov  9 17:44:44 UTC 2001

Modified Files:
        syssrc/sys/arch/arm/xscale: i80312.c i80312reg.h

Log Message:
Disable the ATU interrupt sources (i.e. interrupts that occur when
we get Master or Target aborts).


To generate a diff of this commit:
cvs rdiff -r1.1 -r1.2 syssrc/sys/arch/arm/xscale/i80312.c
cvs rdiff -r1.7 -r1.8 syssrc/sys/arch/arm/xscale/i80312reg.h

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.




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