Module Name:	syssrc
Committed By:	bjh21
Date:		Sat Mar 17 18:12:10 UTC 2001

Modified Files:
	syssrc/sys/arch/arm/arm: undefined.c
	syssrc/sys/arch/arm26/arm26: cpu.c

Log Message:
Create an ARM2-specific undefined-instruction handler which deals with the
undef/SWI bug and handles emulating SWP.

Untested bacuse my ARM2 machine isn't currently set up.


To generate a diff of this commit:
cvs rdiff -r1.7 -r1.8 syssrc/sys/arch/arm/arm/undefined.c
cvs rdiff -r1.9 -r1.10 syssrc/sys/arch/arm26/arm26/cpu.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.