Subject: CVS commit: syssrc
To: None <>
From: Tohru Nishimura <>
List: source-changes
Date: 09/16/2000 08:07:07
Module Name:	syssrc
Committed By:	nisimura
Date:		Sat Sep 16 05:07:07 UTC 2000

Modified Files:
	syssrc/sys/arch/mips/mips: trap.c

Log Message:
There is no need to handle processor master interrupt mask SR_INT_IE
in syscall() anymore.  By defition, processor was in SR_INT_IE turn
on prior to have syscall exception.  MIPS1 assembler hook arranges
to enable the bit for its own.  MIPS3 does the same effect by
turning off EXL bit.

To generate a diff of this commit:
cvs rdiff -r1.146 -r1.147 syssrc/sys/arch/mips/mips/trap.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.