Subject: CVS commit: syssrc
To: None <email@example.com>
From: Tohru Nishimura <firstname.lastname@example.org>
Date: 09/16/2000 07:54:45
Module Name: syssrc
Committed By: nisimura
Date: Sat Sep 16 04:54:45 UTC 2000
- Reimplement MIPS1 cache size dectection logic taking advantage of the
fact the direct mapped cache makes address alias effect.
- Just turn on processor master interrupt mask IEc (SR_INT_IE) bit prior
to call syscall() kernel entry point. IEp is always 1 in this case
To generate a diff of this commit:
cvs rdiff -r1.42 -r1.43 syssrc/sys/arch/mips/mips/locore_mips1.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.