Module Name:	pkgsrc
Committed By:	dmcmahill
Date:		Thu Jun 22 03:15:33 UTC 2000

Modified Files:
	pkgsrc/cad/verilog: Makefile
	pkgsrc/cad/verilog/files: md5 patch-sum
	pkgsrc/cad/verilog/patches: patch-ad
	pkgsrc/cad/verilog/pkg: PLIST
Added Files:
	pkgsrc/cad/verilog/patches: patch-ab
Removed Files:
	pkgsrc/cad/verilog/patches: patch-ae

Log Message:
update to verilog-0.3

Changes, from the authors release statement, are:

This release is a significant improvement over previous releases of
Icarus Verilog, including better language coverage, improved
synthesis, and increased performance.

This release adds to the 0.2 release support for Verilog-2000 style
parameters and parameter overrides, defparam, and localparam,
including proper handling of scoping rules. Also, strength modeling is
added, with support for strengths attached to gates and continuous
assignments.

Combinational user defined primitives have been added to complement
synchronous primitives that were already supported. Support for
primitives should now be fairly complete.

Force/release/assign/deassign syntax now works properly, allowing for
more sophisticated test bench design and debugging.

Bug fixes have been numerous and varied. This release of Icarus
Verilog is considerably more robust then previous versions, thanks to
diligent testing and bug reporting by users all over the world.


To generate a diff of this commit:
cvs rdiff -r1.3 -r1.4 pkgsrc/cad/verilog/Makefile
cvs rdiff -r1.3 -r1.4 pkgsrc/cad/verilog/files/md5 \
    pkgsrc/cad/verilog/files/patch-sum
cvs rdiff -r0 -r1.3 pkgsrc/cad/verilog/patches/patch-ab
cvs rdiff -r1.3 -r1.4 pkgsrc/cad/verilog/patches/patch-ad
cvs rdiff -r1.2 -r0 pkgsrc/cad/verilog/patches/patch-ae
cvs rdiff -r1.1.1.1 -r1.2 pkgsrc/cad/verilog/pkg/PLIST

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.