Module Name:	pkgsrc
Committed By:	dmcmahill
Date:		Sun Apr 30 18:15:18 UTC 2000

Modified Files:
	pkgsrc/cad/verilog-current: Makefile
	pkgsrc/cad/verilog-current/files: md5 patch-sum
	pkgsrc/cad/verilog-current/patches: patch-ad
	pkgsrc/cad/verilog-current/pkg: PLIST
Added Files:
	pkgsrc/cad/verilog-current/patches: patch-aa

Log Message:
Update to verilog-current to the 20000428 snapshot.

The many bug fixes and changes since the last packaged snapshot
are (from the authors announcements):

Icarus Verilog 20000428 Snapshot
--------------------------------
This one clears up some pretty nasty and subtle bugs. If you've been
sending me bug reports, you're probably turning blue holding your breath
in anticipation of this snapshot. Breath in, Breath out.

Hooray, both force and release work properly. I'm happy about that,
release worked out a bit easier then I expected. These should be useful
to test bench designers.

The big news this past week, however, has been bug fixes. Lots of bug
fixes. I got lots of bug reports and I killed pretty nearly all of
them. There were lots of nasty icky problems with passing parameters
to/from tasks, especially when memory words were involved. I fixed up
a whole bunch of these, and now parameter passing should work pretty
will, modulus the few remaining bugs I'm not seeing yet.

The iverilog command is in better shape now, and I encourage people
to use it in place of the older "verilog" driver script. There is a
man page for iverilog, and it supports all the switches needed to do
simulation and synthesis. I would like people to start getting this
driver well tested and the bugs worked out, because it is going to be
the main driver come the next stable release.

Some neat new XNF features are happening. I synthesize identity compare
in XNF, and a few other missing operators. But the really neato part is
that I've taught Icarus Verilog to generate PIN records for module
ports, so that you can make XNF macros out of Verilog source. If you
elaborate a module that has ports, the XNF code generator will automatically
generate the necessary symbols so that external XNF tools can link the
generated output into larger designs. I've compared the XNF files from
Icarus Verilog with those generated by Abel, and they appear the same
to my eyes.

Icarus Verilog 20000421 Snapshot
--------------------------------
Bunches of bug fixes, and a few new features come with this snapshot.
This snapshot makes headway in both simulation and synthesis. I'm
also starting to make a big dent in my todo list for the 0.3 release.

The bunches of little bug fixes in this snapshot are a direct result of
bunches of bug reports this past week that I was able to deal with. If
you've been reporting bugs, this may contain your fix.

I redesigned the process implementation in the vvm backend, so the generated
code is a bit cleaner, and threads are lighter weight. And while I was at
it, fork/join now should work properly. I know there were a bunch of you
out there asking for this, so here it is.

I've incorporated into this release improved runtime support for integer
multiplication, it should now work now matter how incredibly enormous
you make the operands. Thanks to Chris Lattner for contributing the generic
multiply.

I've improved synthesis somewhat, there were some expressions in some
contexts that were not getting synthesized by the -Fsynth functor. This
is fixed, and I'm also starting to add some XNF specific optimizations
into the -Fxnfio functor. I do sensible things with identity compare,
for example.

I've added the program ``iverilog'' to be a new driver program written
in C instead of as a shell script. This driver supports the -tnull,
-txnf and -tvvm targets, as well as the -E flag that causes only the
preprocessor to be run. This should be interesting to those of you who
are looking for a working preprocessor. I'm still working on the -D and
the -I flags, but I expect this program to replace the verilog.sh script
before the 0.3 release.

Icarus Verilog 20000414 Snapshot
--------------------------------
All event handling is now complete. Yet another subject is behind me, and
on I go. By complete, I mean that named events, edge triggers, wait, and
lists of events all work. This took a little longer then I expected, so
some of the other things I wanted to work on had to wait.

As a side effect of event and thread scheduling work, I changed the way
that threads are generated in vvm. The result is that threads should be
a little faster at run time, and a lot faster at compile time. A *LOT*
faster at compile time. (Apparently, Verilog XL is still considerably
faster, but hey, I'm working on it.)


To generate a diff of this commit:
cvs rdiff -r1.3 -r1.4 pkgsrc/cad/verilog-current/Makefile
cvs rdiff -r1.3 -r1.4 pkgsrc/cad/verilog-current/files/md5 \
    pkgsrc/cad/verilog-current/files/patch-sum
cvs rdiff -r0 -r1.1 pkgsrc/cad/verilog-current/patches/patch-aa
cvs rdiff -r1.3 -r1.4 pkgsrc/cad/verilog-current/patches/patch-ad
cvs rdiff -r1.2 -r1.3 pkgsrc/cad/verilog-current/pkg/PLIST

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.