CVS commit: src

[Tohru Nishimura <nisimura%netbsd.org@localhost>]

Module Name:    src
Committed By:   nisimura
Date:           Thu May 20 03:34:07 UTC 1999

Modified Files:
        src/sys/arch/mips/mips: db_interface.c
Log Message:
- Make tlb dump DDB command have 'D' indication for TLB 'dirty bit'.  MIPS
processor is one of processors with no 'referenced bit' nor 'modified bit'
processor machinary.  Those functions are implemented combining two
hardware bits, 'dirty bit' and 'valid bit', with TLBmod exception handler.