thorpej
Thu Feb 22 23:24:47 PST 1996
Update of /a/cvsroot/src/sys/arch/sparc/dev
In directory pain.lcs.mit.edu:/a/var_tmp/cvs-serv20700

Modified Files:
	si.c 
Log Message:
Attempt to work around a hardware bug that screws up DMA on the 4/100.
Apparently, some early 4/100 DMA controllers do illegal memory access on
large ( >= NBPG ) transfers at the end of the transfer.  This appears
as SI_CSR_DMA_BUS_ERR in the csr.  To work around this, we simply
transfer the (up to 3) missing bytes from the bpr.  We were doing this
anyway, so the work-around is to ignore the bus error.

BUT!  I goofed when I implemented the "left-over byte" code for the sw!
It *should* be correct now.  Keep metrics (acceeible via DDB) on the number
of 1, 2, and 3 byte clean-ups, as well as the number of "clean" transfers,
just so we can get a clearer picture.

Thanks to Andrew Gillham <gillham@whirlpool.com> for noticing this!