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[src/trunk]: src/sys/arch/mips Update the FPU register names and bit definiti...



details:   https://anonhg.NetBSD.org/src/rev/03e291faed0e
branches:  trunk
changeset: 379354:03e291faed0e
user:      simonb <simonb%NetBSD.org@localhost>
date:      Sat May 29 12:35:27 2021 +0000

description:
Update the FPU register names and bit definitions to something somewhat
modern (MIPS32/MIPS64) and convert to __BIT/__BITS.

diffstat:

 sys/arch/mips/include/cpuregs.h   |   63 +++++-----
 sys/arch/mips/mips/fp.S           |  226 +++++++++++++++++++-------------------
 sys/arch/mips/mips/locore.S       |   18 +-
 sys/arch/mips/mips/mips_emul.c    |    6 +-
 sys/arch/mips/mips/mips_fpu.c     |   10 +-
 sys/arch/mips/mips/mips_fputrap.c |   14 +-
 6 files changed, 170 insertions(+), 167 deletions(-)

diffs (truncated from 844 to 300 lines):

diff -r 23ae52bb09a9 -r 03e291faed0e sys/arch/mips/include/cpuregs.h
--- a/sys/arch/mips/include/cpuregs.h   Sat May 29 12:25:08 2021 +0000
+++ b/sys/arch/mips/include/cpuregs.h   Sat May 29 12:35:27 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpuregs.h,v 1.110 2021/03/17 11:05:37 simonb Exp $     */
+/*     $NetBSD: cpuregs.h,v 1.111 2021/05/29 12:35:27 simonb Exp $     */
 
 /*
  * Copyright (c) 2009 Miodrag Vallat.
@@ -704,40 +704,41 @@
 /*
  * The floating point version and status registers.
  */
-#define        MIPS_FPU_ID     $0
-#define        MIPS_FPU_CSR    $31
+#define        MIPS_FIR        $0      /* FP Implementation and Revision Register */
+#define        MIPS_FCSR       $31     /* FP Control/Status Register */
 
 /*
  * The floating point coprocessor status register bits.
  */
-#define        MIPS_FPU_ROUNDING_BITS          0x00000003
-#define        MIPS_FPU_ROUND_RN               0x00000000
-#define        MIPS_FPU_ROUND_RZ               0x00000001
-#define        MIPS_FPU_ROUND_RP               0x00000002
-#define        MIPS_FPU_ROUND_RM               0x00000003
-#define        MIPS_FPU_STICKY_BITS            0x0000007c
-#define        MIPS_FPU_STICKY_INEXACT         0x00000004
-#define        MIPS_FPU_STICKY_UNDERFLOW       0x00000008
-#define        MIPS_FPU_STICKY_OVERFLOW        0x00000010
-#define        MIPS_FPU_STICKY_DIV0            0x00000020
-#define        MIPS_FPU_STICKY_INVALID         0x00000040
-#define        MIPS_FPU_ENABLE_BITS            0x00000f80
-#define        MIPS_FPU_ENABLE_INEXACT         0x00000080
-#define        MIPS_FPU_ENABLE_UNDERFLOW       0x00000100
-#define        MIPS_FPU_ENABLE_OVERFLOW        0x00000200
-#define        MIPS_FPU_ENABLE_DIV0            0x00000400
-#define        MIPS_FPU_ENABLE_INVALID         0x00000800
-#define        MIPS_FPU_EXCEPTION_BITS         0x0003f000
-#define        MIPS_FPU_EXCEPTION_INEXACT      0x00001000
-#define        MIPS_FPU_EXCEPTION_UNDERFLOW    0x00002000
-#define        MIPS_FPU_EXCEPTION_OVERFLOW     0x00004000
-#define        MIPS_FPU_EXCEPTION_DIV0         0x00008000
-#define        MIPS_FPU_EXCEPTION_INVALID      0x00010000
-#define        MIPS_FPU_EXCEPTION_UNIMPL       0x00020000
-#define        MIPS_FPU_COND_BIT               0x00800000
-#define        MIPS_FPU_FLUSH_BIT              0x01000000      /* r4k,  MBZ on r3k */
-#define        MIPS1_FPC_MBZ_BITS              0xff7c0000
-#define        MIPS3_FPC_MBZ_BITS              0xfe7c0000
+#define        MIPS_FCSR_RM            __BITS(1,0)
+#define          MIPS_FCSR_RM_RN         0     /* round to nearest */
+#define          MIPS_FCSR_RM_RZ         1     /* round toward zerO */
+#define          MIPS_FCSR_RM_RP         2     /* round towards +infinity */
+#define          MIPS_FCSR_RM_RM         3     /* round towards -infinity */
+#define        MIPS_FCSR_FLAGS         __BITS(6,2)
+#define          MIPS_FCSR_FLAGS_I       __BIT(2)      /* inexact */
+#define          MIPS_FCSR_FLAGS_U       __BIT(3)      /* underflow */
+#define          MIPS_FCSR_FLAGS_O       __BIT(4)      /* overflow */
+#define          MIPS_FCSR_FLAGS_Z       __BIT(5)      /* divide by zero */
+#define          MIPS_FCSR_FLAGS_V       __BIT(6)      /* invalid operation */
+#define        MIPS_FCSR_ENABLES       __BITS(11,7)
+#define          MIPS_FCSR_ENABLES_I     __BIT(7)      /* inexact */
+#define          MIPS_FCSR_ENABLES_U     __BIT(8)      /* underflow */
+#define          MIPS_FCSR_ENABLES_O     __BIT(9)      /* overflow */
+#define          MIPS_FCSR_ENABLES_Z     __BIT(10)     /* divide by zero */
+#define          MIPS_FCSR_ENABLES_V     __BIT(11)     /* invalid operation */
+#define        MIPS_FCSR_CAUSE         __BITS(17,12)
+#define          MIPS_FCSR_CAUSE_I       __BIT(12)     /* inexact */
+#define          MIPS_FCSR_CAUSE_U       __BIT(13)     /* underflow */
+#define          MIPS_FCSR_CAUSE_O       __BIT(14)     /* overflow */
+#define          MIPS_FCSR_CAUSE_Z       __BIT(15)     /* divide by zero */
+#define          MIPS_FCSR_CAUSE_V       __BIT(16)     /* invalid operation */
+#define          MIPS_FCSR_CAUSE_E       __BIT(17)     /* unimplemented operation */
+#define        MIPS_FCSR_NAN_2008      __BIT(18)
+#define        MIPS_FCSR_ABS_2008      __BIT(19)
+#define        MIPS_FCSR_FCC0          __BIT(23)
+#define        MIPS_FCSR_FCC           (MIPS_FPU_COND_BIT | __BITS(31,25))
+#define        MIPS_FCSR_FS            __BIT(24)       /* r4k+ */
 
 
 /*
diff -r 23ae52bb09a9 -r 03e291faed0e sys/arch/mips/mips/fp.S
--- a/sys/arch/mips/mips/fp.S   Sat May 29 12:25:08 2021 +0000
+++ b/sys/arch/mips/mips/fp.S   Sat May 29 12:35:27 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: fp.S,v 1.57 2021/05/24 07:27:39 simonb Exp $   */
+/*     $NetBSD: fp.S,v 1.58 2021/05/29 12:35:27 simonb Exp $   */
 
 /*
  * Copyright (c) 1992, 1993
@@ -143,10 +143,10 @@ NESTED(mips_emul_fp, CALLFRAME_SIZ, ra)
        PTR_L   a3, fmt_tbl(v0)                 # switch on FUNC & FMT
        INT_L   a2, PCB_FPREGS+FRAME_FSR(t0)
 #else
-       cfc1    a2, MIPS_FPU_CSR                # get exception register
+       cfc1    a2, MIPS_FCSR                   # get exception register
        PTR_L   a3, fmt_tbl(v0)                 # switch on FUNC & FMT
-       and     a2, a2, ~MIPS_FPU_EXCEPTION_BITS        # clear exception
-       ctc1    a2, MIPS_FPU_CSR
+       and     a2, a2, ~MIPS_FCSR_CAUSE        # clear exception
+       ctc1    a2, MIPS_FCSR
 #endif
        j       a3
 
@@ -809,17 +809,17 @@ branchc1_tbl:
        .text
 
 bcfalse:
-       li      v0, MIPS_FPU_COND_BIT
+       li      v0, MIPS_FCSR_FCC0
        and     v0, v0, a2
        beq     v0, zero, bcemul_branch
        b       done
 bctrue:
-       li      v0, MIPS_FPU_COND_BIT
+       li      v0, MIPS_FCSR_FCC0
        and     v0, v0, a2
        bne     v0, zero, bcemul_branch
        b       done
 bcfalse_l:
-       li      v0, MIPS_FPU_COND_BIT
+       li      v0, MIPS_FCSR_FCC0
        and     v0, v0, a2
        beq     v0, zero, bcemul_branch
        REG_PROLOGUE
@@ -829,7 +829,7 @@ bcfalse_l:
        REG_EPILOGUE
        b       done
 bctrue_l:
-       li      v0, MIPS_FPU_COND_BIT
+       li      v0, MIPS_FCSR_FCC0
        and     v0, v0, a2
        bne     v0, zero, bcemul_branch
        REG_PROLOGUE
@@ -899,8 +899,8 @@ 2:
 3:
        bne     ta1, zero, result_ft_s          # if FT != 0, result=FT
        bne     ta2, zero, result_ft_s
-       and     v0, a2, MIPS_FPU_ROUNDING_BITS  # get rounding mode
-       bne     v0, MIPS_FPU_ROUND_RM, 1f       # round to -infinity?
+       and     v0, a2, MIPS_FCSR_RM            # get rounding mode
+       bne     v0, MIPS_FCSR_RM_RM, 1f         # round to -infinity?
        or      t0, t0, ta0                     # compute result sign
        b       result_fs_s
 1:
@@ -958,8 +958,8 @@ 1:
        bne     t2, ta2, 2f                     # if same, result=0
        move    t1, zero                        # result=0
        move    t2, zero
-       and     v0, a2, MIPS_FPU_ROUNDING_BITS  # get rounding mode
-       bne     v0, MIPS_FPU_ROUND_RM, 1f       # round to -infinity?
+       and     v0, a2, MIPS_FCSR_RM            # get rounding mode
+       bne     v0, MIPS_FCSR_RM_RM, 1f         # round to -infinity?
        or      t0, t0, ta0                     # compute result sign
        b       result_fs_s
 1:
@@ -1022,8 +1022,8 @@ 3:
        bne     ta1, zero, result_ft_d          # if FT != 0, result=FT
        bne     ta2, zero, result_ft_d
        bne     ta3, zero, result_ft_d
-       and     v0, a2, MIPS_FPU_ROUNDING_BITS  # get rounding mode
-       bne     v0, MIPS_FPU_ROUND_RM, 1f       # round to -infinity?
+       and     v0, a2, MIPS_FCSR_RM            # get rounding mode
+       bne     v0, MIPS_FCSR_RM_RM, 1f         # round to -infinity?
        or      t0, t0, ta0                     # compute result sign
        b       result_fs_d
 1:
@@ -1116,8 +1116,8 @@ 1:
        move    t1, zero                        # result=0
        move    t2, zero
        move    t3, zero
-       and     v0, a2, MIPS_FPU_ROUNDING_BITS  # get rounding mode
-       bne     v0, MIPS_FPU_ROUND_RM, 1f       # round to -infinity?
+       and     v0, a2, MIPS_FCSR_RM            # get rounding mode
+       bne     v0, MIPS_FCSR_RM_RM, 1f         # round to -infinity?
        or      t0, t0, ta0                     # compute result sign
        b       result_fs_d
 1:
@@ -1312,15 +1312,15 @@ 2:
 3:
        bne     ta1, zero, 2f                   # is FT zero?
        bne     ta2, zero, 1f
-       or      a2, a2, MIPS_FPU_EXCEPTION_DIV0 | MIPS_FPU_STICKY_DIV0
-       and     v0, a2, MIPS_FPU_ENABLE_DIV0    # trap enabled?
+       or      a2, a2, MIPS_FCSR_CAUSE_Z | MIPS_FCSR_FLAGS_Z
+       and     v0, a2, MIPS_FCSR_ENABLES_Z     # trap enabled?
        bne     v0, zero, fpe_trap
 #ifdef FPEMUL
        PTR_L   t1, L_PCB(MIPS_CURLWP)          # get pcb of current lwp
        #nop
        INT_S   a2, PCB_FPREGS+FRAME_FSR(t1)
 #else
-       ctc1    a2, MIPS_FPU_CSR                # save exceptions
+       ctc1    a2, MIPS_FCSR                   # save exceptions
 #endif
        li      t1, SEXP_INF                    # result is infinity
        move    t2, zero
@@ -1392,15 +1392,15 @@ 3:
        bne     ta1, zero, 2f                   # is FT zero?
        bne     ta2, zero, 1f
        bne     ta3, zero, 1f
-       or      a2, a2, MIPS_FPU_EXCEPTION_DIV0 | MIPS_FPU_STICKY_DIV0
-       and     v0, a2, MIPS_FPU_ENABLE_DIV0    # trap enabled?
+       or      a2, a2, MIPS_FCSR_CAUSE_Z | MIPS_FCSR_FLAGS_Z
+       and     v0, a2, MIPS_FCSR_ENABLES_Z     # trap enabled?
        bne     v0, zero, fpe_trap
 #ifdef FPEMUL
        PTR_L   t1, L_PCB(MIPS_CURLWP)          # get pcb of current lwp
        #nop
        INT_S   a2, PCB_FPREGS+FRAME_FSR(t1)
 #else
-       ctc1    a2, MIPS_FPU_CSR                # save exceptions
+       ctc1    a2, MIPS_FCSR                   # save exceptions
 #endif
        li      t1, DEXP_INF                    # result is infinity
        move    t2, zero
@@ -1912,7 +1912,7 @@ 2:
  * Convert single to integer.
  */
 cvt_w_s:
-       and     v1, a2, MIPS_FPU_ROUNDING_BITS  # get rounding mode
+       and     v1, a2, MIPS_FCSR_RM            # get rounding mode
 _cvt_w_s:
        jal     _C_LABEL(get_fs_s)
        bne     t1, SEXP_INF, 1f                # is FS an infinity?
@@ -1933,7 +1933,7 @@ 1:
  * Convert double to integer.
  */
 cvt_w_d:
-       and     v1, a2, MIPS_FPU_ROUNDING_BITS  # get rounding mode
+       and     v1, a2, MIPS_FCSR_RM            # get rounding mode
 _cvt_w_d:
        jal     _C_LABEL(get_fs_d)
        bne     t1, DEXP_INF, 1f                # is FS an infinity?
@@ -1954,8 +1954,8 @@ cvt_w:
        blt     t1, WEXP_MIN, underflow_w       # is exponent too small?
 #else
        bge     t1, WEXP_MIN, 3f                # is exponent too small?
-       beq     v1, MIPS_FPU_ROUND_RP, 1f       # round to +infinity
-       beq     v1, MIPS_FPU_ROUND_RM, 2f       # round to -infinity
+       beq     v1, MIPS_FCSR_RM_RP, 1f         # round to +infinity
+       beq     v1, MIPS_FCSR_RM_RM, 2f         # round to -infinity
 
        move    t2, zero
        b       result_fs_w
@@ -2002,10 +2002,10 @@ 1:
  * round result (t0 is sign, t2 is integer part, t3 is fractional part).
  */
 2:
-       and     v0, a2, MIPS_FPU_ROUNDING_BITS  # get rounding mode
-       beq     v0, MIPS_FPU_ROUND_RN, 3f       # round to nearest
-       beq     v0, MIPS_FPU_ROUND_RZ, 5f       # round to zero (truncate)
-       beq     v0, MIPS_FPU_ROUND_RP, 1f       # round to +infinity
+       and     v0, a2, MIPS_FCSR_RM            # get rounding mode
+       beq     v0, MIPS_FCSR_RM_RN, 3f         # round to nearest
+       beq     v0, MIPS_FCSR_RM_RZ, 5f         # round to zero (truncate)
+       beq     v0, MIPS_FCSR_RM_RP, 1f         # round to +infinity
        beq     t0, zero, 5f                    # if sign is positive, truncate
        b       2f
 1:
@@ -2034,15 +2034,15 @@ 1:
  * Handle inexact exception.
  */
 inexact_w:
-       or      a2, a2, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
-       and     v0, a2, MIPS_FPU_ENABLE_INEXACT
+       or      a2, a2, MIPS_FCSR_CAUSE_I | MIPS_FCSR_FLAGS_I
+       and     v0, a2, MIPS_FCSR_ENABLES_I
        bne     v0, zero, fpe_trap
 #ifdef FPEMUL
        PTR_L   v0, L_PCB(MIPS_CURLWP)          # get pcb of current lwp
        #nop
        INT_S   a2, PCB_FPREGS+FRAME_FSR(v0)
 #else
-       ctc1    a2, MIPS_FPU_CSR                # save exceptions
+       ctc1    a2, MIPS_FCSR                   # save exceptions
 #endif
        b       result_fs_w
 
@@ -2052,10 +2052,10 @@ inexact_w:
  * or generate an invalid exception.
  */
 overflow_w:
-       or      a2, a2, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW
-       and     v0, a2, MIPS_FPU_ENABLE_OVERFLOW
+       or      a2, a2, MIPS_FCSR_CAUSE_O | MIPS_FCSR_FLAGS_O
+       and     v0, a2, MIPS_FCSR_ENABLES_O
        bne     v0, zero, fpe_trap
-       and     v0, a2, MIPS_FPU_ENABLE_INEXACT
+       and     v0, a2, MIPS_FCSR_ENABLES_I
        bne     v0, zero, inexact_w             # inexact traps enabled?
        b       invalid_w
 
@@ -2065,10 +2065,10 @@ overflow_w:
  * or generate an invalid exception.
  */
 underflow_w:
-       or      a2, a2, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
-       and     v0, a2, MIPS_FPU_ENABLE_UNDERFLOW
+       or      a2, a2, MIPS_FCSR_CAUSE_U | MIPS_FCSR_FLAGS_U



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