[src/trunk]: src/sys/arch/x86/include Add AMD CPUID Fn0000_0008 %ebx bit 3 IN...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/dffa3de1ede1
branches:  trunk
changeset: 373553:dffa3de1ede1
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Fri Feb 17 09:53:24 2023 +0000

description:
Add AMD CPUID Fn0000_0008 %ebx bit 3 INVLPGB.

diffstat:

 sys/arch/x86/include/specialreg.h |  5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diffs (26 lines):

diff -r c6f59c6e4dec -r dffa3de1ede1 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Fri Feb 17 06:34:46 2023 +0000
+++ b/sys/arch/x86/include/specialreg.h Fri Feb 17 09:53:24 2023 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.202 2023/02/14 15:46:06 msaitoh Exp $ */
+/*     $NetBSD: specialreg.h,v 1.203 2023/02/17 09:53:24 msaitoh Exp $ */
 
 /*
  * Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -868,6 +868,7 @@
 #define CPUID_CAPEX_CLZERO        __BIT(0)  /* CLZERO instruction */
 #define CPUID_CAPEX_IRPERF        __BIT(1)  /* InstRetCntMsr */
 #define CPUID_CAPEX_XSAVEERPTR    __BIT(2)  /* RstrFpErrPtrs by XRSTOR */
+#define CPUID_CAPEX_INVLPGB       __BIT(3)  /* INVLPGB instruction */
 #define CPUID_CAPEX_RDPRU         __BIT(4)  /* RDPRU instruction */
 #define CPUID_CAPEX_MBE                   __BIT(6)  /* Memory Bandwidth Enforcement */
 #define CPUID_CAPEX_MCOMMIT       __BIT(8)  /* MCOMMIT instruction */
@@ -890,7 +891,7 @@
 #define CPUID_CAPEX_BTC_NO        __BIT(29) /* Branch Type Confusion NO */
 
 #define CPUID_CAPEX_FLAGS      "\20"                                      \
-       "\1CLZERO"      "\2IRPERF"      "\3XSAVEERPTR"                     \
+       "\1CLZERO"      "\2IRPERF"      "\3XSAVEERPTR"  "\4INVLPGB"        \
        "\5RDPRU"                       "\7MBE"                            \
        "\11MCOMMIT"    "\12WBNOINVD"   "\13B10"                           \
        "\15IBPB"       "\16INT_WBINVD" "\17IBRS"       "\20STIBP"         \