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[src/netbsd-10]: src/sys/arch/next68k Pull up following revision(s) (requeste...
details: https://anonhg.NetBSD.org/src/rev/ee3f65b6c381
branches: netbsd-10
changeset: 373478:ee3f65b6c381
user: martin <martin%NetBSD.org@localhost>
date: Sun Feb 12 11:48:56 2023 +0000
description:
Pull up following revision(s) (requested by tsutsui in ticket #77):
sys/arch/next68k/include/vmparam.h: revision 1.29
sys/arch/next68k/next68k/machdep.c: revision 1.118
sys/arch/next68k/include/param.h: revision 1.13
sys/arch/next68k/next68k/pmap_bootstrap.c: revision 1.45
sys/arch/next68k/next68k/locore.s: revision 1.70
sys/arch/next68k/next68k/locore.s: revision 1.71
Use explicit CPU strings and remove hp300 derived stuff.
Remove #ifdef'ed out hp300 specific stuff.
Remove leftover "last kernel PT page" settings derived from hp300.
Whilehere, also remove VM definitions for obsolete COMPAT_HPUX stuff.
All hp300 machines has RAMs at a region from the highest address
i.e. 0xFFFFFFFF to smaller address (as HP claims "it's the MSB first"),
so kernels have to prepare PA==KVA mappings as the "last PT page" to
guarantee the running kernel works both before and after the MMU is
turned on. For such a special mapping, we have to set up necessary
segment table and page table during early startup, in pmap_bootstrap()
invoked from locore.s.
On the other hand, NeXT machines have RAMs at a region from 0x40000000
to below (i.e. to larger address) so we still need a PA==KVA mapping.
However currently NetBSD/next68k just uses the transparent translation
registers to achieve the PA==KVA mapping, so unlike hp300 we don't have
to prepare special segment table and page table for it.
Note many other m68k ports (like luna68k, news68k, x68k etc.) have
RAMs at a region from 0x00000000 so usually we can assume PA==KVA
and don't have to bother to prepare such speicial mappings.
No user visible changes (except now freed wasted pages for the tables).
Tested on my NeXTstation slab.
diffstat:
sys/arch/next68k/include/param.h | 4 +-
sys/arch/next68k/include/vmparam.h | 16 +---
sys/arch/next68k/next68k/locore.s | 115 ++---------------------------
sys/arch/next68k/next68k/machdep.c | 48 +++--------
sys/arch/next68k/next68k/pmap_bootstrap.c | 63 ++--------------
5 files changed, 40 insertions(+), 206 deletions(-)
diffs (truncated from 530 to 300 lines):
diff -r 093934994b6c -r ee3f65b6c381 sys/arch/next68k/include/param.h
--- a/sys/arch/next68k/include/param.h Wed Feb 08 18:28:10 2023 +0000
+++ b/sys/arch/next68k/include/param.h Sun Feb 12 11:48:56 2023 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: param.h,v 1.12 2012/02/10 17:35:48 para Exp $ */
+/* $NetBSD: param.h,v 1.12.78.1 2023/02/12 11:48:56 martin Exp $ */
/*
* Copyright (c) 1988 University of Utah.
@@ -50,7 +50,7 @@
#define PGSHIFT 12 /* LOG2(NBPG) */
#define KERNBASE 0x00000000 /* start of kernel virtual */
-#define UPAGES 3 /* pages of u-area */
+#define UPAGES 2 /* pages of u-area */
#include <m68k/param.h>
diff -r 093934994b6c -r ee3f65b6c381 sys/arch/next68k/include/vmparam.h
--- a/sys/arch/next68k/include/vmparam.h Wed Feb 08 18:28:10 2023 +0000
+++ b/sys/arch/next68k/include/vmparam.h Sun Feb 12 11:48:56 2023 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: vmparam.h,v 1.28 2021/12/05 04:54:21 msaitoh Exp $ */
+/* $NetBSD: vmparam.h,v 1.28.4.1 2023/02/12 11:48:56 martin Exp $ */
/*
* This file was taken from mvme68k/include/vmparam.h and
@@ -59,16 +59,8 @@
/*
* USRSTACK is the top (end) of the user stack.
- *
- * NOTE: the ONLY reason that HIGHPAGES is 0x100 instead of UPAGES (3)
- * is for HPUX compatibility. Why?? Because HPUX's debuggers
- * have the user's stack hard-wired at FFF00000 for post-mortems,
- * and we must be compatible...
*/
-#define USRSTACK (-HIGHPAGES*PAGE_SIZE) /* Start of user stack */
-#define BTOPUSRSTACK (0x100000-HIGHPAGES) /* btop(USRSTACK) */
-#define P1PAGES 0x100000
-#define HIGHPAGES (0x100000/PAGE_SIZE)
+#define USRSTACK VM_MAXUSER_ADDRESS /* Start of user stack */
/*
* Virtual memory related constants, all in bytes
@@ -106,7 +98,7 @@
#define VM_MAXUSER_ADDRESS ((vaddr_t)0xFFF00000)
#define VM_MAX_ADDRESS ((vaddr_t)0xFFF00000)
#define VM_MIN_KERNEL_ADDRESS ((vaddr_t)0)
-#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)(0-PAGE_SIZE*NPTEPG*2))
+#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)(0-PAGE_SIZE*NPTEPG))
/* virtual sizes (bytes) for various kernel submaps */
#define VM_PHYS_SIZE (USRIOSIZE*PAGE_SIZE)
@@ -131,4 +123,4 @@
struct pv_header *pvheader; /* pv table for this seg */
};
-#endif /* _MVME68K_VMPARAM_H_ */
+#endif /* _NEXT68K_VMPARAM_H_ */
diff -r 093934994b6c -r ee3f65b6c381 sys/arch/next68k/next68k/locore.s
--- a/sys/arch/next68k/next68k/locore.s Wed Feb 08 18:28:10 2023 +0000
+++ b/sys/arch/next68k/next68k/locore.s Sun Feb 12 11:48:56 2023 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.68 2022/05/30 09:56:03 andvar Exp $ */
+/* $NetBSD: locore.s,v 1.68.4.1 2023/02/12 11:48:56 martin Exp $ */
/*
* Copyright (c) 1998 Darrin B. Jewell
@@ -229,10 +229,6 @@
movl #CPU_68040,%a0@ | and a 68040 CPU
RELOC(fputype, %a0)
movl #FPU_68040,%a0@ | ...and FPU
-#if defined(ENABLE_HP_CODE)
- RELOC(ectype, %a0)
- movl #EC_NONE,%a0@ | and no cache (for now XXX)
-#endif
RELOC(machineid, %a0)
movl #40,%a0@ | @@@ useless
jra Lstart1
@@ -324,20 +320,16 @@
* Prepare to enable MMU.
* Since the kernel is not mapped logical == physical we must insure
* that when the MMU is turned on, all prefetched addresses (including
- * the PC) are valid. In order guarantee that, we use the last physical
- * page (which is conveniently mapped == VA) and load it up with enough
- * code to defeat the prefetch, then we execute the jump back to here.
- *
- * Is this all really necessary, or am I paranoid??
+ * the PC) are valid. In order guarantee that, we use the transparent
+ * translation registers (which provide PA == VA mappings) and just
+ * turns on the MMU, then jump from the VA == PA address (at 0x40XXXXXX)
+ * to the actual kernel virtual address (at 0x00XXXXXX) code via a far
+ * jump instruction so that we can defeat the prefetch.
*/
RELOC(Sysseg_pa, %a0) | system segment table addr
movl %a0@,%d1 | read value (a PA)
RELOC(mmutype, %a0)
-#if defined(ENABLE_HP_CODE)
- tstl %a0@ | HP MMU?
- jeq Lhpmmu2 | yes, skip
-#endif
cmpl #MMU_68040,%a0@ | 68040?
jne Lmotommu1 | no, skip
.long 0x4e7b1807 | movc %d1,%srp
@@ -349,31 +341,7 @@
pmove %a0@,%srp | load the supervisor root pointer
movl #0x80000002,%a0@ | reinit upper half for CRP loads
-#if defined(ENABLE_HP_CODE)
- jra Lstploaddone | done
-Lhpmmu2:
- moveq #PGSHIFT,%d2
- lsrl %d2,%d1 | convert to page frame
- movl %d1,INTIOBASE+MMUBASE+MMUSSTP | load in sysseg table register
-#endif
Lstploaddone:
-#if defined(ENABLE_MAXADDR_TRAMPOLINE)
- lea MAXADDR,%a2 | PA of last RAM page
- ASRELOC(Lhighcode, %a1) | addr of high code
- ASRELOC(Lehighcode, %a3) | end addr
-Lcodecopy:
- movw %a1@+,%a2@+ | copy a word
- cmpl %a3,%a1 | done yet?
- jcs Lcodecopy | no, keep going
- jmp MAXADDR | go for it!
- /*
- * BEGIN MMU TRAMPOLINE. This section of code is not
- * executed in-place. It's copied to the last page
- * of RAM (mapped va == pa) and executed there.
- */
-
-Lhighcode:
-#endif /* ENABLE_MAXADDR_TRAMPOLINE */
/*
* Set up the vector table, and race to get the MMU
@@ -387,21 +355,12 @@
movc %d0,%vbr
RELOC(mmutype, %a0)
-#if defined(ENABLE_HP_CODE)
- tstl %a0@ | HP MMU?
- jeq Lhpmmu3 | yes, skip
-#endif
cmpl #MMU_68040,%a0@ | 68040?
jne Lmotommu2 | no, skip
-#if defined(ENABLE_HP_CODE)
- movw #0,INTIOBASE+MMUBASE+MMUCMD+2
- movw #MMU_IEN+MMU_CEN+MMU_FPE,INTIOBASE+MMUBASE+MMUCMD+2
- | enable FPU and caches
-#endif
- | This is a hack to get PA=KVA when turning on MMU
- | it will only work on 68040's. We should fix something
- | to boot 68030's later.
+ | This is a hack to get PA=KVA when turning on MMU as mentioned above.
+ | Currintly this will only work on 68040's. We should also provide
+ | %tt0 and %tt1 settings to boot 68030's later.
movel #0x0200c040,%d0 | intio devices are at 0x02000000
.long 0x4e7b0004 | movc %d0,%itt0
.long 0x4e7b0006 | movc %d0,%dtt0
@@ -425,28 +384,11 @@
.long 0x4e7b0007 | movc %d0,%dtt1
jmp Lenab1
Lmotommu2:
-#if defined(ENABLE_HP_CODE)
- movl #MMU_IEN+MMU_FPE,INTIOBASE+MMUBASE+MMUCMD
- | enable 68881 and i-cache
-#endif
pflusha
RELOC(prototc, %a2)
movl #0x82c0aa00,%a2@ | value to load TC with
pmove %a2@,%tc | load it
jmp Lenab1:l | force absolute (not pc-relative) jmp
-#if defined(ENABLE_HP_CODE)
-Lhpmmu3:
- movl #0,INTIOBASE+MMUBASE+MMUCMD | clear external cache
- movl #MMU_ENAB,INTIOBASE+MMUBASE+MMUCMD | turn on MMU
- jmp Lenab1:l | jmp to mapped code
-#endif
-#if defined(ENABLE_MAXADDR_TRAMPOLINE)
-Lehighcode:
-
- /*
- * END MMU TRAMPOLINE. Address register %a5 is now free.
- */
-#endif
/*
* Should be running mapped from this point on
@@ -478,7 +420,7 @@
movc %d0,%cacr | clear cache(s)
jra Lenab3
Ltbia040:
- .word 0xf518
+ .word 0xf518 | pflusha
Lenab3:
jbsr _C_LABEL(next68k_init)
@@ -941,24 +883,6 @@
rts
#endif
-#if defined(ENABLE_HP_CODE)
-ENTRY(ecacheon)
- tstl _C_LABEL(ectype)
- jeq Lnocache7
- MMUADDR(%a0)
- orl #MMU_CEN,%a0@(MMUCMD)
-Lnocache7:
- rts
-
-ENTRY(ecacheoff)
- tstl _C_LABEL(ectype)
- jeq Lnocache8
- MMUADDR(%a0)
- andl #~MMU_CEN,%a0@(MMUCMD)
-Lnocache8:
- rts
-#endif
-
/*
* Load a new user segment table pointer.
*/
@@ -1137,11 +1061,6 @@
GLOBAL(cputype)
.long 0xdeadbeef | default to 68020 CPU
-#if defined(ENABLE_HP_CODE)
-GLOBAL(ectype)
- .long EC_NONE | external cache type, default to none
-#endif
-
GLOBAL(fputype)
.long 0xdeadbeef | default to 68882 FPU
@@ -1175,20 +1094,6 @@
GLOBAL(monbootflag)
.long 0
-#if defined(ENABLE_HP_CODE)
-GLOBAL(extiobase)
- .long 0 | KVA of base of external IO space
-
-GLOBAL(CLKbase)
- .long 0 | KVA of base of clock registers
-
-GLOBAL(MMUbase)
- .long 0 | KVA of base of HP MMU registers
-
-GLOBAL(pagezero)
- .long 0 | PA of first page of kernel text
-#endif
-
#ifdef USELEDS
ASLOCAL(heartbeat)
.long 0 | clock ticks since last pulse of heartbeat
diff -r 093934994b6c -r ee3f65b6c381 sys/arch/next68k/next68k/machdep.c
--- a/sys/arch/next68k/next68k/machdep.c Wed Feb 08 18:28:10 2023 +0000
+++ b/sys/arch/next68k/next68k/machdep.c Sun Feb 12 11:48:56 2023 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.116.4.1 2023/02/01 18:55:11 martin Exp $ */
+/* $NetBSD: machdep.c,v 1.116.4.2 2023/02/12 11:48:56 martin Exp $ */
/*
* Copyright (c) 1998 Darrin B. Jewell
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.116.4.1 2023/02/01 18:55:11 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.116.4.2 2023/02/12 11:48:56 martin Exp $");
#include "opt_ddb.h"
#include "opt_kgdb.h"
@@ -321,7 +321,7 @@
void
identifycpu(void)
{
- const char *mc, *mmu_str, *fpu_str, *cache_str;
+ const char *cpu_str, *mmu_str, *fpu_str, *cache_str;
extern int turbo;
/*
@@ -329,21 +329,23 @@
*/
switch (cputype) {
case CPU_68040:
- mc = "40";
+ cpu_str = "MC68040";
cpuspeed = turbo ? 33 : 25;
delay_divisor = 759 / cpuspeed;
break;
case CPU_68030:
- mc = "30";
+ cpu_str = "MC68030";
cpuspeed = 25;
delay_divisor = 2048 / cpuspeed;
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