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[src/trunk]: src/sys/dev/ic Modify comment. Whitespace. No functional change.
details: https://anonhg.NetBSD.org/src/rev/f3da2661582c
branches: trunk
changeset: 372947:f3da2661582c
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Sat Jan 07 03:22:02 2023 +0000
description:
Modify comment. Whitespace. No functional change.
diffstat:
sys/dev/ic/igpioreg.h | 424 +++++++++++++++++++++++++-------------------------
1 files changed, 212 insertions(+), 212 deletions(-)
diffs (truncated from 582 to 300 lines):
diff -r 3e904ed8730f -r f3da2661582c sys/dev/ic/igpioreg.h
--- a/sys/dev/ic/igpioreg.h Sat Jan 07 02:13:05 2023 +0000
+++ b/sys/dev/ic/igpioreg.h Sat Jan 07 03:22:02 2023 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: igpioreg.h,v 1.4 2023/01/07 02:13:05 msaitoh Exp $ */
+/* $NetBSD: igpioreg.h,v 1.5 2023/01/07 03:22:02 msaitoh Exp $ */
/*
* Copyright (c) 2021 Emmanuel Dreyfus
@@ -99,7 +99,7 @@
{ "INT344B", 1, 48, 119, 0x100, 0x120 },
{ "INT344B", 2, 120, 151, 0x100, 0x120 },
- /* Sunrisepoint-H */
+ /* Coffee Lake-S (Same as Sunrisepoint-H(INT345D)) */
{ "INT3451", 0, 0, 47, 0x100, 0x120 },
{ "INT3451", 1, 48, 180, 0x100, 0x120 },
{ "INT3451", 2, 181, 191, 0x100, 0x120 },
@@ -117,25 +117,25 @@
{ "INT33C7", 0, 0, 94, 0x000, 0x000 },
{ "INT3437", 0, 0, 94, 0x000, 0x000 },
- /* Cannonlake-H */
+ /* Cannon Lake-H */
{ "INT3450", 0, 0, 50, 0x100, 0x120 },
{ "INT3450", 1, 51, 154, 0x100, 0x120 },
{ "INT3450", 2, 155, 248, 0x100, 0x120 },
{ "INT3450", 3, 249, 298, 0x100, 0x120 },
- /* Cannonlake-LP */
+ /* Cannon Lake-LP */
{ "INT34BB", 0, 0, 67, 0x100, 0x120 },
{ "INT34BB", 1, 68, 180, 0x100, 0x120 },
{ "INT34BB", 2, 181, 243, 0x100, 0x120 },
- /* Alderlake */
+ /* Alder Lake-S */
{ "INTC1056", 0, 0, 94, 0x200, 0x220 },
{ "INTC1056", 1, 95, 150, 0x200, 0x220 },
{ "INTC1056", 2, 151, 199, 0x200, 0x220 },
{ "INTC1056", 3, 200, 269, 0x200, 0x220 },
{ "INTC1056", 4, 270, 303, 0x200, 0x220 },
- /* Icelake */
+ /* Ice Lake-LP */
{ "INT3455", 0, 0, 58, 0x100, 0x110 },
{ "INT3455", 1, 59, 152, 0x100, 0x110 },
{ "INT3455", 2, 153, 215, 0x100, 0x110 },
@@ -147,32 +147,32 @@
{ "INT34C4", 2, 149, 237, 0x100, 0x110 },
{ "INT34C4", 3, 238, 266, 0x100, 0x110 },
- /* Tigerlake-LP */
+ /* Tiger Lake-LP */
{ "INT34C5", 0, 0, 66, 0x100, 0x120 },
{ "INT34C5", 1, 67, 170, 0x100, 0x120 },
{ "INT34C5", 2, 171, 259, 0x100, 0x120 },
{ "INT34C5", 3, 260, 276, 0x100, 0x120 },
- /* Tigerlake-LP */
- { "INTC1055", 0, 0, 66, 0x100, 0x120 },
- { "INTC1055", 1, 67, 170, 0x100, 0x120 },
- { "INTC1055", 2, 171, 259, 0x100, 0x120 },
- { "INTC1055", 3, 260, 276, 0x100, 0x120 },
+ /* Alder Lake-P (Same as Tigerlake-LP(INT34C5)) */
+ { "INTC1055", 0, 0, 66, 0x100, 0x120 },
+ { "INTC1055", 1, 67, 170, 0x100, 0x120 },
+ { "INTC1055", 2, 171, 259, 0x100, 0x120 },
+ { "INTC1055", 3, 260, 276, 0x100, 0x120 },
- /* Tigerlake-LP */
- { "INTC1057", 0, 0, 66, 0x100, 0x120 },
- { "INTC1057", 1, 67, 170, 0x100, 0x120 },
- { "INTC1057", 2, 171, 259, 0x100, 0x120 },
- { "INTC1057", 3, 260, 276, 0x100, 0x120 },
+ /* Tiger Lake-LP */
+ { "INTC1057", 0, 0, 66, 0x100, 0x120 },
+ { "INTC1057", 1, 67, 170, 0x100, 0x120 },
+ { "INTC1057", 2, 171, 259, 0x100, 0x120 },
+ { "INTC1057", 3, 260, 276, 0x100, 0x120 },
- /* Tigerlake-H */
+ /* Tiger Lake-H */
{ "INT34C6", 0, 0, 78, 0x100, 0x120 },
{ "INT34C6", 1, 79, 180, 0x100, 0x120 },
{ "INT34C6", 2, 181, 217, 0x100, 0x120 },
{ "INT34C6", 3, 218, 266, 0x100, 0x120 },
{ "INT34C6", 4, 267, 290, 0x100, 0x120 },
- /* Jasperlake */
+ /* Jasper Lake */
{ "INT34C8", 0, 0, 91, 0x100, 0x120 },
{ "INT34C8", 1, 92, 194, 0x100, 0x120 },
{ "INT34C8", 2, 195, 224, 0x100, 0x120 },
@@ -186,22 +186,22 @@
{ "INT3536", 5, 179, 246, 0x100, 0x110 },
/* Emmitsburg */
- { "INTC1071", 0, 0, 65, 0x200, 0x210 },
- { "INTC1071", 1, 66, 111, 0x200, 0x210 },
- { "INTC1071", 2, 112, 145, 0x200, 0x210 },
- { "INTC1071", 3, 146, 183, 0x200, 0x210 },
- { "INTC1071", 4, 184, 261, 0x200, 0x210 },
+ { "INTC1071", 0, 0, 65, 0x200, 0x210 },
+ { "INTC1071", 1, 66, 111, 0x200, 0x210 },
+ { "INTC1071", 2, 112, 145, 0x200, 0x210 },
+ { "INTC1071", 3, 146, 183, 0x200, 0x210 },
+ { "INTC1071", 4, 184, 261, 0x200, 0x210 },
/* Denverton */
- { "INTC3000", 0, 0, 40, 0x100, 0x120 },
- { "INTC3000", 1, 41, 153, 0x100, 0x120 },
+ { "INTC3000", 0, 0, 40, 0x100, 0x120 },
+ { "INTC3000", 1, 41, 153, 0x100, 0x120 },
/* Cedarfork */
- { "INTC3001", 0, 0, 167, 0x200, 0x230 },
- { "INTC3001", 1, 168, 236, 0x200, 0x230 },
+ { "INTC3001", 0, 0, 167, 0x200, 0x230 },
+ { "INTC3001", 1, 168, 236, 0x200, 0x230 },
- /* Geminilake */
- { "INT3453", 0, 0, 34, 0x100, 0x110 },
+ /* Gemini Lake */
+ { "INT3453", 0, 0, 34, 0x100, 0x110 },
#ifdef notyet
/*
@@ -210,156 +210,156 @@
/* Broxton */
{ "apollolake-pinctrl", 0, 0, 0, 0x100, 0x110 },
{ "broxton-pinctrl", 0, 0, 0, 0x100, 0x110 },
- { "INT34D1", 0, 0, 0, 0x100, 0x110 },
- { "INT3452", 0, 0, 0, 0x100, 0x110 },
+ { "INT34D1", 0, 0, 0, 0x100, 0x110 },
+ { "INT3452", 0, 0, 0, 0x100, 0x110 },
/* Cherryview */
- { "INT33FF", 0, 0, 0, 0x000, 0x000 },
+ { "INT33FF", 0, 0, 0, 0x000, 0x000 },
#endif
- { NULL, 0, 0, 0, 0x000, 0x000 },
+ { NULL, 0, 0, 0, 0x000, 0x000 },
};
struct igpio_pin_group igpio_pin_group[] = {
/* Sunrisepoint-LP */
- { "INT344B", 0, 151, "A" },
+ { "INT344B", 0, 151, "A" },
+
+ /* Coffee Lake-S (Same as Sunrisepoint-H(INT345D)) */
+ { "INT3451", 0, 0, "A" },
+ { "INT3451", 1, 24, "B" },
+ { "INT3451", 0, 48, "C" },
+ { "INT3451", 1, 72, "D" },
+ { "INT3451", 2, 96, "E" },
+ { "INT3451", 3, 109, "F" },
+ { "INT3451", 4, 133, "G" },
+ { "INT3451", 5, 157, "H" },
+ { "INT3451", 0, 181, "I" },
/* Sunrisepoint-H */
- { "INT3451", 0, 0, "A" },
- { "INT3451", 1, 24, "B" },
- { "INT3451", 0, 48, "C" },
- { "INT3451", 1, 72, "D" },
- { "INT3451", 2, 96, "E" },
- { "INT3451", 3, 109, "F" },
- { "INT3451", 4, 133, "G" },
- { "INT3451", 5, 157, "H" },
- { "INT3451", 0, 181, "I" },
-
- /* Sunrisepoint-H */
- { "INT345D", 0, 0, "A" },
- { "INT345D", 1, 24, "B" },
- { "INT345D", 0, 48, "C" },
- { "INT345D", 1, 72, "D" },
- { "INT345D", 2, 96, "E" },
- { "INT345D", 3, 109, "F" },
- { "INT345D", 4, 133, "G" },
- { "INT345D", 5, 157, "H" },
- { "INT345D", 0, 181, "I" },
+ { "INT345D", 0, 0, "A" },
+ { "INT345D", 1, 24, "B" },
+ { "INT345D", 0, 48, "C" },
+ { "INT345D", 1, 72, "D" },
+ { "INT345D", 2, 96, "E" },
+ { "INT345D", 3, 109, "F" },
+ { "INT345D", 4, 133, "G" },
+ { "INT345D", 5, 157, "H" },
+ { "INT345D", 0, 181, "I" },
/* Baytrail */
- { "INT33B2", 0, 101, "A" },
+ { "INT33B2", 0, 101, "A" },
/* Lynxpoint */
- { "INT33C7", 0, 94, "A" },
- { "INT3437", 0, 94, "A" },
+ { "INT33C7", 0, 94, "A" },
+ { "INT3437", 0, 94, "A" },
- /* Cannonlake-H */
- { "INT3450", 0, 0, "GPP_A" },
- { "INT3450", 1, 25, "GPP_B" },
- { "INT3450", 0, 51, "GPP_C" },
- { "INT3450", 1, 75, "GPP_D" },
- { "INT3450", 2, 99, "GPP_G" },
- { "INT3450", 3, 107, "AZA" },
- { "INT3450", 4, 115, "vGPIO_0" },
- { "INT3450", 5, 147, "vGPIO_1" },
- { "INT3450", 0, 155, "GPP_K" },
- { "INT3450", 1, 179, "GPP_H" },
- { "INT3450", 2, 203, "GPP_E" },
- { "INT3450", 3, 216, "GPP_F" },
- { "INT3450", 4, 240, "SPI" },
- { "INT3450", 0, 249, "CPU" },
- { "INT3450", 1, 260, "JTAG" },
- { "INT3450", 2, 269, "GPP_I" },
- { "INT3450", 3, 287, "GPP_J" },
+ /* Cannon Lake-H */
+ { "INT3450", 0, 0, "GPP_A" },
+ { "INT3450", 1, 25, "GPP_B" },
+ { "INT3450", 0, 51, "GPP_C" },
+ { "INT3450", 1, 75, "GPP_D" },
+ { "INT3450", 2, 99, "GPP_G" },
+ { "INT3450", 3, 107, "AZA" },
+ { "INT3450", 4, 115, "vGPIO_0" },
+ { "INT3450", 5, 147, "vGPIO_1" },
+ { "INT3450", 0, 155, "GPP_K" },
+ { "INT3450", 1, 179, "GPP_H" },
+ { "INT3450", 2, 203, "GPP_E" },
+ { "INT3450", 3, 216, "GPP_F" },
+ { "INT3450", 4, 240, "SPI" },
+ { "INT3450", 0, 249, "CPU" },
+ { "INT3450", 1, 260, "JTAG" },
+ { "INT3450", 2, 269, "GPP_I" },
+ { "INT3450", 3, 287, "GPP_J" },
- /* Cannonlake-LP */
- { "INT34BB", 0, 0, "GPP_A" },
- { "INT34BB", 1, 25, "GPP_B" },
- { "INT34BB", 2, 51, "GPP_G" },
- { "INT34BB", 3, 59, "SPI" },
- { "INT34BB", 0, 68, "GPP_D" },
- { "INT34BB", 1, 93, "GPP_F" },
- { "INT34BB", 2, 117, "GPP_H" },
- { "INT34BB", 3, 141, "vGPIO" },
- { "INT34BB", 4, 173, "vGPIO" },
- { "INT34BB", 0, 181, "GPP_C" },
- { "INT34BB", 1, 205, "GPP_E" },
- { "INT34BB", 2, 229, "JTAG" },
- { "INT34BB", 3, 238, "HVCMOS" },
+ /* Cannon Lake-LP */
+ { "INT34BB", 0, 0, "GPP_A" },
+ { "INT34BB", 1, 25, "GPP_B" },
+ { "INT34BB", 2, 51, "GPP_G" },
+ { "INT34BB", 3, 59, "SPI" },
+ { "INT34BB", 0, 68, "GPP_D" },
+ { "INT34BB", 1, 93, "GPP_F" },
+ { "INT34BB", 2, 117, "GPP_H" },
+ { "INT34BB", 3, 141, "vGPIO" },
+ { "INT34BB", 4, 173, "vGPIO" },
+ { "INT34BB", 0, 181, "GPP_C" },
+ { "INT34BB", 1, 205, "GPP_E" },
+ { "INT34BB", 2, 229, "JTAG" },
+ { "INT34BB", 3, 238, "HVCMOS" },
- /* Alderlake */
- { "INTC1056", 0, 0, "GPP_I" },
+ /* Alder Lake-S */
+ { "INTC1056", 0, 0, "GPP_I" },
{ "INTC1056", 1, 25, "GPP_R" },
{ "INTC1056", 2, 48, "GPP_J" },
{ "INTC1056", 3, 60, "vGPIO" },
{ "INTC1056", 4, 87, "vGPIO_0" },
{ "INTC1056", 0, 95, "GPP_B" },
- { "INTC1056", 1, 119, "GPP_G" },
- { "INTC1056", 2, 127, "GPP_H" },
- { "INTC1056", 0, 151, "SPI0" },
- { "INTC1056", 1, 160, "GPP_A" },
- { "INTC1056", 2, 176, "GPP_C" },
- { "INTC1056", 0, 200, "GPP_S" },
- { "INTC1056", 1, 208, "GPP_E" },
- { "INTC1056", 2, 231, "GPP_K" },
- { "INTC1056", 3, 246, "GPP_F" },
- { "INTC1056", 0, 270, "GPP_D" },
- { "INTC1056", 1, 295, "JTAG" },
+ { "INTC1056", 1, 119, "GPP_G" },
+ { "INTC1056", 2, 127, "GPP_H" },
+ { "INTC1056", 0, 151, "SPI0" },
+ { "INTC1056", 1, 160, "GPP_A" },
+ { "INTC1056", 2, 176, "GPP_C" },
+ { "INTC1056", 0, 200, "GPP_S" },
+ { "INTC1056", 1, 208, "GPP_E" },
+ { "INTC1056", 2, 231, "GPP_K" },
+ { "INTC1056", 3, 246, "GPP_F" },
+ { "INTC1056", 0, 270, "GPP_D" },
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