[src/trunk]: src/sys/arch Explicitly disable overflow interrupts before enabl...

[ryo <ryo%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/76c89a832a0b
branches:  trunk
changeset: 372721:76c89a832a0b
user:      ryo <ryo%NetBSD.org@localhost>
date:      Thu Dec 22 06:58:07 2022 +0000

description:
Explicitly disable overflow interrupts before enabling the cycle counter.

diffstat:

 sys/arch/aarch64/aarch64/cpu.c  |  5 +++--
 sys/arch/arm/arm/cpufunc.c      |  5 +++--
 sys/arch/arm/arm32/arm32_boot.c |  5 +++--
 3 files changed, 9 insertions(+), 6 deletions(-)

diffs (78 lines):

diff -r 5a13298ab59c -r 76c89a832a0b sys/arch/aarch64/aarch64/cpu.c
--- a/sys/arch/aarch64/aarch64/cpu.c    Thu Dec 22 02:52:35 2022 +0000
+++ b/sys/arch/aarch64/aarch64/cpu.c    Thu Dec 22 06:58:07 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.70 2022/05/29 16:14:41 ryo Exp $ */
+/* $NetBSD: cpu.c,v 1.71 2022/12/22 06:58:07 ryo Exp $ */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.70 2022/05/29 16:14:41 ryo Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.71 2022/12/22 06:58:07 ryo Exp $");
 
 #include "locators.h"
 #include "opt_arm_debug.h"
@@ -499,6 +499,7 @@
        }
 
        reg_pmcr_el0_write(PMCR_E | PMCR_C);
+       reg_pmintenclr_el1_write(PMINTEN_C | PMINTEN_P);
        reg_pmcntenset_el0_write(PMCNTEN_C);
 
        const uint32_t prev = cpu_counter32();
diff -r 5a13298ab59c -r 76c89a832a0b sys/arch/arm/arm/cpufunc.c
--- a/sys/arch/arm/arm/cpufunc.c        Thu Dec 22 02:52:35 2022 +0000
+++ b/sys/arch/arm/arm/cpufunc.c        Thu Dec 22 06:58:07 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc.c,v 1.184 2022/05/16 07:07:17 skrll Exp $      */
+/*     $NetBSD: cpufunc.c,v 1.185 2022/12/22 06:58:07 ryo Exp $        */
 
 /*
  * arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.184 2022/05/16 07:07:17 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.185 2022/12/22 06:58:07 ryo Exp $");
 
 #include "opt_arm_start.h"
 #include "opt_compat_netbsd.h"
@@ -1964,6 +1964,7 @@
                 * Start and reset the PMC Cycle Counter.
                 */
                armreg_pmcr_write(ARM11_PMCCTL_E | ARM11_PMCCTL_P | ARM11_PMCCTL_C);
+               armreg_pmintenclr_write(PMINTEN_C | PMINTEN_P);
                armreg_pmcntenset_write(CORTEX_CNTENS_C);
                return 0;
        }
diff -r 5a13298ab59c -r 76c89a832a0b sys/arch/arm/arm32/arm32_boot.c
--- a/sys/arch/arm/arm32/arm32_boot.c   Thu Dec 22 02:52:35 2022 +0000
+++ b/sys/arch/arm/arm32/arm32_boot.c   Thu Dec 22 06:58:07 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: arm32_boot.c,v 1.44 2021/10/31 16:23:47 skrll Exp $    */
+/*     $NetBSD: arm32_boot.c,v 1.45 2022/12/22 06:58:08 ryo Exp $      */
 
 /*
  * Copyright (c) 2002, 2003, 2005  Genetec Corporation.  All rights reserved.
@@ -122,7 +122,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.44 2021/10/31 16:23:47 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: arm32_boot.c,v 1.45 2022/12/22 06:58:08 ryo Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_cputypes.h"
@@ -407,6 +407,7 @@
                 * Start and reset the PMC Cycle Counter.
                 */
                armreg_pmcr_write(ARM11_PMCCTL_E|ARM11_PMCCTL_P|ARM11_PMCCTL_C);
+               armreg_pmintenclr_write(PMINTEN_C | PMINTEN_P);
                armreg_pmcntenset_write(CORTEX_CNTENS_C);
        }
 #endif