[src/trunk]: src/sys/dev/tprof PMCR.E should not be disabled from tprof.

[ryo <ryo%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/b6cb1756dd58
branches:  trunk
changeset: 372476:b6cb1756dd58
user:      ryo <ryo%NetBSD.org@localhost>
date:      Thu Dec 01 00:29:10 2022 +0000

description:
PMCR.E should not be disabled from tprof.

PMCR.E controls not only performance event counters but also the cycle
counter operation, and the cycle counter may be used for cpu_counter.
Similarly, the 31st bit in PMINTENCLR and PMCNTENCLR controls the cycle
counter, not performance event counters, and should not be modified.

diffstat:

 sys/arch/aarch64/include/armreg.h |   8 +++++++-
 sys/dev/tprof/tprof_armv7.c       |  22 +++++++++-------------
 sys/dev/tprof/tprof_armv8.c       |   9 ++++-----
 3 files changed, 20 insertions(+), 19 deletions(-)

diffs (135 lines):

diff -r 9947feb9d5f7 -r b6cb1756dd58 sys/arch/aarch64/include/armreg.h
--- a/sys/arch/aarch64/include/armreg.h Thu Dec 01 00:27:59 2022 +0000
+++ b/sys/arch/aarch64/include/armreg.h Thu Dec 01 00:29:10 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.61 2022/05/02 10:13:15 skrll Exp $ */
+/* $NetBSD: armreg.h,v 1.62 2022/12/01 00:29:10 ryo Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -1250,10 +1250,16 @@
 AARCH64REG_WRITE_INLINE(pmintenclr_el1)
 AARCH64REG_WRITE_INLINE(pmintenset_el1)
 
+#define PMINTEN_C              __BIT(31)       // for the cycle counter
+#define PMINTEN_P              __BITS(30,0)    // for event counters (0-30)
+
 AARCH64REG_WRITE_INLINE(pmovsclr_el0)
 AARCH64REG_READ_INLINE(pmovsset_el0)
 AARCH64REG_WRITE_INLINE(pmovsset_el0)
 
+#define PMOVS_C                        __BIT(31)       // for the cycle counter
+#define PMOVS_P                        __BITS(30,0)    // for event counters (0-30)
+
 AARCH64REG_WRITE_INLINE(pmselr_el0)
 
 AARCH64REG_WRITE_INLINE(pmswinc_el0)
diff -r 9947feb9d5f7 -r b6cb1756dd58 sys/dev/tprof/tprof_armv7.c
--- a/sys/dev/tprof/tprof_armv7.c       Thu Dec 01 00:27:59 2022 +0000
+++ b/sys/dev/tprof/tprof_armv7.c       Thu Dec 01 00:29:10 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_armv7.c,v 1.7 2022/11/01 11:03:01 jmcneill Exp $ */
+/* $NetBSD: tprof_armv7.c,v 1.8 2022/12/01 00:29:10 ryo Exp $ */
 
 /*-
  * Copyright (c) 2018 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tprof_armv7.c,v 1.7 2022/11/01 11:03:01 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tprof_armv7.c,v 1.8 2022/12/01 00:29:10 ryo Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -45,6 +45,11 @@
 #define        PMCR_D                  __BIT(3)
 #define        PMCR_E                  __BIT(0)
 
+#define        PMINTEN_C               __BIT(31)
+#define        PMINTEN_P               __BITS(30,0)
+#define        PMCNTEN_C               __BIT(31)
+#define        PMCNTEN_P               __BITS(30,0)
+
 #define        PMEVTYPER_P             __BIT(31)
 #define        PMEVTYPER_U             __BIT(30)
 #define        PMEVTYPER_EVTCOUNT      __BITS(7,0)
@@ -161,18 +166,12 @@
 armv7_pmu_stop_cpu(void *arg1, void *arg2)
 {
        const uint32_t counter_mask = __BIT(armv7_pmu_counter);
-       uint32_t pmcr;
 
        /* Disable overflow interrupts */
        armreg_pmintenclr_write(counter_mask);
 
        /* Disable event counter */
        armreg_pmcntenclr_write(counter_mask);
-
-       /* Disable performance monitor */
-       pmcr = armreg_pmcr_read();
-       pmcr &= ~PMCR_E;
-       armreg_pmcr_write(pmcr);
 }
 
 static uint64_t
@@ -266,13 +265,10 @@
        armreg_pmuserenr_write(0);
 
        /* Disable interrupts */
-       armreg_pmintenclr_write(~0U);
+       armreg_pmintenclr_write(PMINTEN_P);
 
        /* Disable counters */
-       armreg_pmcntenclr_write(~0U);
-
-       /* Disable performance monitor */
-       armreg_pmcr_write(0);
+       armreg_pmcntenclr_write(PMCNTEN_P);
 
        return tprof_backend_register("tprof_armv7", &tprof_armv7_pmu_ops,
            TPROF_BACKEND_VERSION);
diff -r 9947feb9d5f7 -r b6cb1756dd58 sys/dev/tprof/tprof_armv8.c
--- a/sys/dev/tprof/tprof_armv8.c       Thu Dec 01 00:27:59 2022 +0000
+++ b/sys/dev/tprof/tprof_armv8.c       Thu Dec 01 00:29:10 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tprof_armv8.c,v 1.16 2022/11/10 07:54:20 ryo Exp $ */
+/* $NetBSD: tprof_armv8.c,v 1.17 2022/12/01 00:29:10 ryo Exp $ */
 
 /*-
  * Copyright (c) 2018 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tprof_armv8.c,v 1.16 2022/11/10 07:54:20 ryo Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tprof_armv8.c,v 1.17 2022/12/01 00:29:10 ryo Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -112,7 +112,7 @@
 
        /* Enable event counter */
        reg_pmcntenset_el0_write(counter_mask);
-       reg_pmcr_el0_write(PMCR_E);
+       reg_pmcr_el0_write(reg_pmcr_el0_read() | PMCR_E);
 }
 
 static void
@@ -125,7 +125,6 @@
 
        /* Disable event counter */
        reg_pmcntenclr_el0_write(counter_mask);
-       reg_pmcr_el0_write(0);
 }
 
 static uint64_t
@@ -214,7 +213,7 @@
        reg_pmuserenr_el0_write(0);
 
        /* Disable interrupts */
-       reg_pmintenclr_el1_write(~0U);
+       reg_pmintenclr_el1_write(PMINTEN_P);
 
        /* Disable event counters */
        reg_pmcntenclr_el0_write(PMCNTEN_P);