[src/trunk]: src/usr.sbin/cpuctl/arch Add CPUID Fn8000_0021 AMD Extended Feat...

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/b266e50f0513
branches:  trunk
changeset: 372336:b266e50f0513
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Wed Nov 16 14:01:41 2022 +0000

description:
Add CPUID Fn8000_0021 AMD Extended Features Identification 2.

diffstat:

 sys/arch/x86/include/specialreg.h |  25 ++++++++++++++++++++++++-
 usr.sbin/cpuctl/arch/i386.c       |  10 ++++++++--
 2 files changed, 32 insertions(+), 3 deletions(-)

diffs (70 lines):

diff -r 0784f7dceb97 -r b266e50f0513 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Wed Nov 16 13:15:26 2022 +0000
+++ b/sys/arch/x86/include/specialreg.h Wed Nov 16 14:01:41 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: specialreg.h,v 1.195 2022/11/16 13:14:33 msaitoh Exp $ */
+/*     $NetBSD: specialreg.h,v 1.196 2022/11/16 14:01:41 msaitoh Exp $ */
 
 /*
  * Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -986,6 +986,29 @@
        "\35SvsmCommPageMSR" "\36NestedVirtSnpMsr"
 
 /*
+ * AMD Extended Features 2.
+ * CPUID Fn8000_0021
+ */
+
+/* %eax */
+#define CPUID_AMDEXT2_NONESTEDDBP __BIT(0) /* No nested data breakpoints */
+#define CPUID_AMDEXT2_LFENCESERIAL __BIT(2) /* LFENCE always serializing */
+#define CPUID_AMDEXT2_SMMPGCFGLCK __BIT(3) /* SMM Paging configuration lock */
+#define CPUID_AMDEXT2_NULLSELCLRB __BIT(6) /* Null segment selector clr base */
+#define CPUID_AMDEXT2_UPADDRIGN          __BIT(7) /* Upper Address Ignore */
+#define CPUID_AMDEXT2_AUTOIBRS   __BIT(8) /* Automatic IBRS */
+#define CPUID_AMDEXT2_NOSMMCTL   __BIT(9) /* SMM_CTL MSR is not supported */
+#define CPUID_AMDEXT2_PREFETCHCTL __BIT(13) /* Prefetch control MSR */
+#define CPUID_AMDEXT2_CPUIDUSRDIS __BIT(17) /* CPUID dis. for non-priv. soft */
+
+#define CPUID_AMDEXT2_FLAGS     "\20"                                        \
+       "\1NoNestedDataBp"      "\3LfenceAlwaysSerialize" "\4SmmPgCfgLock"    \
+                            "\7NullSelectClearsBase" "\10UpperAddressIgnore" \
+       "\11AutomaticIBRS" "\12NoSmmCtlMSR"                                   \
+                       "\16PrefetchCtlMSR"                                   \
+                       "\22CpuidUserDis"
+
+/*
  * Centaur Extended Feature flags.
  */
 #define CPUID_VIA_HAS_RNG      0x00000004      /* Random number generator */
diff -r 0784f7dceb97 -r b266e50f0513 usr.sbin/cpuctl/arch/i386.c
--- a/usr.sbin/cpuctl/arch/i386.c       Wed Nov 16 13:15:26 2022 +0000
+++ b/usr.sbin/cpuctl/arch/i386.c       Wed Nov 16 14:01:41 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: i386.c,v 1.129 2022/11/16 13:15:26 msaitoh Exp $       */
+/*     $NetBSD: i386.c,v 1.130 2022/11/16 14:01:41 msaitoh Exp $       */
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -57,7 +57,7 @@
 
 #include <sys/cdefs.h>
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.129 2022/11/16 13:15:26 msaitoh Exp $");
+__RCSID("$NetBSD: i386.c,v 1.130 2022/11/16 14:01:41 msaitoh Exp $");
 #endif /* not lint */
 
 #include <sys/types.h>
@@ -2232,6 +2232,12 @@
        }
 
        if (cpu_vendor == CPUVENDOR_AMD) {
+               if (ci->ci_max_ext_cpuid >= 0x80000021) {
+                       x86_cpuid(0x80000021, descs);
+                       print_bits(cpuname, "AMD Extended features 2",
+                           CPUID_AMDEXT2_FLAGS, descs[0]);
+               }
+
                if (ci->ci_max_ext_cpuid >= 0x80000007) {
                        x86_cpuid(0x80000007, descs);
                        print_bits(cpuname, "RAS features",