[src/trunk]: src/sys/arch/arm/xilinx Add I2C clocks

[jmcneill <jmcneill%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/b3ef93a28cf1
branches:  trunk
changeset: 372268:b3ef93a28cf1
user:      jmcneill <jmcneill%NetBSD.org@localhost>
date:      Sat Nov 05 17:28:55 2022 +0000

description:
Add I2C clocks

diffstat:

 sys/arch/arm/xilinx/zynq7000_clkc.c |  16 +++++++++++++---
 1 files changed, 13 insertions(+), 3 deletions(-)

diffs (51 lines):

diff -r 3135dd139224 -r b3ef93a28cf1 sys/arch/arm/xilinx/zynq7000_clkc.c
--- a/sys/arch/arm/xilinx/zynq7000_clkc.c       Sat Nov 05 11:33:55 2022 +0000
+++ b/sys/arch/arm/xilinx/zynq7000_clkc.c       Sat Nov 05 17:28:55 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq7000_clkc.c,v 1.3 2022/10/26 22:14:22 jmcneill Exp $ */
+/* $NetBSD: zynq7000_clkc.c,v 1.4 2022/11/05 17:28:55 jmcneill Exp $ */
 
 /*-
  * Copyright (c) 2022 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -28,7 +28,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(0, "$NetBSD: zynq7000_clkc.c,v 1.3 2022/10/26 22:14:22 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq7000_clkc.c,v 1.4 2022/11/05 17:28:55 jmcneill Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -56,6 +56,8 @@
 #define        APER_CLK_CTRL   0x12c
 #define         UART1_CPU_1XCLKACT     __BIT(21)
 #define         UART0_CPU_1XCLKACT     __BIT(20)
+#define         I2C1_CPU_1XCLKACT      __BIT(19)
+#define         I2C0_CPU_1XCLKACT      __BIT(18)
 #define         SDI1_CPU_1XCLKACT      __BIT(11)
 #define         SDI0_CPU_1XCLKACT      __BIT(10)
 #define        SDIO_CLK_CTRL   0x150
@@ -246,7 +248,9 @@
                   clk == &sc->sc_clk[clkid_uart1]) {
                return zynq7000_clkc_get_rate_iop(sc, UART_CLK_CTRL);
        } else if (clk == &sc->sc_clk[clkid_uart0_aper] ||
-                  clk == &sc->sc_clk[clkid_uart1_aper]) {
+                  clk == &sc->sc_clk[clkid_uart1_aper] ||
+                  clk == &sc->sc_clk[clkid_i2c0_aper] ||
+                  clk == &sc->sc_clk[clkid_i2c1_aper]) {
                return zynq7000_clkc_clk_get_rate(sc,
                    &sc->sc_clk[clkid_cpu_1x]);
        } else {
@@ -298,6 +302,12 @@
        } else if (clk == &sc->sc_clk[clkid_uart1_aper]) {
                reg = APER_CLK_CTRL;
                mask = UART1_CPU_1XCLKACT;
+       } else if (clk == &sc->sc_clk[clkid_i2c0_aper]) {
+               reg = APER_CLK_CTRL;
+               mask = I2C0_CPU_1XCLKACT;
+       } else if (clk == &sc->sc_clk[clkid_i2c1_aper]) {
+               reg = APER_CLK_CTRL;
+               mask = I2C1_CPU_1XCLKACT;
        } else {
                return ENXIO;
        }