[src/trunk]: src/sys/arch/riscv/riscv In bus_space_write_{1,2,4,8} store the ...

[simonb <simonb%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/70acecee933a
branches:  trunk
changeset: 372215:70acecee933a
user:      simonb <simonb%NetBSD.org@localhost>
date:      Mon Oct 31 12:50:49 2022 +0000

description:
In bus_space_write_{1,2,4,8} store the correct register in write to device.

diffstat:

 sys/arch/riscv/riscv/bus_space_generic.S |  12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diffs (54 lines):

diff -r 47dc13e9507d -r 70acecee933a sys/arch/riscv/riscv/bus_space_generic.S
--- a/sys/arch/riscv/riscv/bus_space_generic.S  Mon Oct 31 12:49:18 2022 +0000
+++ b/sys/arch/riscv/riscv/bus_space_generic.S  Mon Oct 31 12:50:49 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: bus_space_generic.S,v 1.2 2022/10/31 12:49:18 simonb Exp $     */
+/*     $NetBSD: bus_space_generic.S,v 1.3 2022/10/31 12:50:49 simonb Exp $     */
 
 /*-
  * Copyright (c) 2022 The NetBSD Foundation, Inc.
@@ -33,7 +33,7 @@
 #include <riscv/asm.h>
 #include "assym.h"
 
-RCSID("$NetBSD: bus_space_generic.S,v 1.2 2022/10/31 12:49:18 simonb Exp $")
+RCSID("$NetBSD: bus_space_generic.S,v 1.3 2022/10/31 12:50:49 simonb Exp $")
 
 
 /* void bs_c_1(a0: tag, a1: src, srcoffset, dst, dstoffset, count); */
@@ -245,7 +245,7 @@
        PTR_L   a5, BS_STRIDE(a0)       /* stride */
        PTR_SLL a2, a2, a5              /* offset <<= stride */
        PTR_ADD a2, a2, a1              /* add to address */
-       sb      a0, 0(a2)               /* store 8-bit */
+       sb      a3, 0(a2)               /* store 8-bit */
        ret
 END(generic_bs_w_1)
 
@@ -255,7 +255,7 @@
        PTR_L   a5, BS_STRIDE(a0)       /* stride */
        PTR_SLL a2, a2, a5              /* offset <<= stride */
        PTR_ADD a2, a2, a1              /* add to address */
-       sh      a0 ,0(a2)               /* store 16-bit */
+       sh      a3 ,0(a2)               /* store 16-bit */
        ret
 END(generic_bs_w_2)
 
@@ -265,7 +265,7 @@
        PTR_L   a5, BS_STRIDE(a0)       /* stride */
        PTR_SLL a2, a2, a5              /* offset <<= stride */
        PTR_ADD a2, a2, a1              /* add to address */
-       sw      a0, 0(a2)               /* store 32-bit */
+       sw      a3, 0(a2)               /* store 32-bit */
        ret
 END(generic_bs_w_4)
 
@@ -276,7 +276,7 @@
        PTR_L   a5, BS_STRIDE(a0)       /* stride */
        PTR_SLL a2, a2, a5              /* offset <<= stride */
        PTR_ADD a2, a2, a1              /* add to address */
-       sd      a0, 0(a2)               /* store 64-bit */
+       sd      a3, 0(a2)               /* store 64-bit */
        ret
 END(generic_bs_w_8)
 #endif