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[src/trunk]: src/sys/arch Retire PARALLELLA and ZEDBOARD kernel configs.
details: https://anonhg.NetBSD.org/src/rev/cd1073597062
branches: trunk
changeset: 372140:cd1073597062
user: jmcneill <jmcneill%NetBSD.org@localhost>
date: Fri Oct 28 20:37:03 2022 +0000
description:
Retire PARALLELLA and ZEDBOARD kernel configs.
The Zynq-7000 port has been converted to Devicetree and is supported
by the GENERIC kernel now.
diffstat:
sys/arch/arm/xilinx/zynq_platform.c | 6 +-
sys/arch/arm/zynq/files.zynq | 55 -
sys/arch/arm/zynq/zynq7000_board.c | 133 --
sys/arch/arm/zynq/zynq7000_intr.h | 103 -
sys/arch/arm/zynq/zynq7000_reg.h | 65 -
sys/arch/arm/zynq/zynq7000_sdhc.c | 119 -
sys/arch/arm/zynq/zynq7000_uart.c | 64 -
sys/arch/arm/zynq/zynq7000_usb.c | 81 -
sys/arch/arm/zynq/zynq7000_var.h | 98 -
sys/arch/arm/zynq/zynq_axi.c | 150 --
sys/arch/arm/zynq/zynq_cemac.c | 86 -
sys/arch/arm/zynq/zynq_dma.c | 46 -
sys/arch/arm/zynq/zynq_slcr.c | 309 ----
sys/arch/arm/zynq/zynq_slcrreg.h | 187 --
sys/arch/arm/zynq/zynq_slcrvar.h | 62 -
sys/arch/arm/zynq/zynq_space.c | 258 ---
sys/arch/arm/zynq/zynq_uart.c | 2184 ---------------------------------
sys/arch/arm/zynq/zynq_uartreg.h | 110 -
sys/arch/arm/zynq/zynq_uartvar.h | 55 -
sys/arch/arm/zynq/zynq_usb.c | 374 -----
sys/arch/arm/zynq/zynq_usbreg.h | 112 -
sys/arch/arm/zynq/zynq_usbvar.h | 68 -
sys/arch/evbarm/Makefile | 4 +-
sys/arch/evbarm/conf/PARALLELLA | 102 -
sys/arch/evbarm/conf/README.evbarm | 4 +-
sys/arch/evbarm/conf/ZEDBOARD | 99 -
sys/arch/evbarm/conf/files.parallella | 4 -
sys/arch/evbarm/conf/files.zedboard | 4 -
sys/arch/evbarm/conf/files.zynq | 9 -
sys/arch/evbarm/conf/mk.zynq | 33 -
sys/arch/evbarm/conf/std.zynq | 33 -
sys/arch/evbarm/zynq/platform.h | 57 -
sys/arch/evbarm/zynq/zynq_machdep.c | 354 -----
33 files changed, 5 insertions(+), 5423 deletions(-)
diffs (truncated from 5608 to 300 lines):
diff -r 6cccb2dc47ea -r cd1073597062 sys/arch/arm/xilinx/zynq_platform.c
--- a/sys/arch/arm/xilinx/zynq_platform.c Fri Oct 28 09:44:52 2022 +0000
+++ b/sys/arch/arm/xilinx/zynq_platform.c Fri Oct 28 20:37:03 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: zynq_platform.c,v 1.8 2022/10/27 20:37:10 jmcneill Exp $ */
+/* $NetBSD: zynq_platform.c,v 1.9 2022/10/28 20:37:03 jmcneill Exp $ */
/*-
* Copyright (c) 2019 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
#include "arml2cc.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: zynq_platform.c,v 1.8 2022/10/27 20:37:10 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: zynq_platform.c,v 1.9 2022/10/28 20:37:03 jmcneill Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -75,7 +75,7 @@
#define ZYNQ_ARMCORE_VBASE (ZYNQ_GPV_VBASE + ZYNQ_GPV_SIZE)
#define ZYNQ_ARMCORE_PBASE 0xf8f00000
-#define ZYNQ_ARMCORE_SIZE 0x00003000
+#define ZYNQ_ARMCORE_SIZE 0x00100000
#define ZYNQ_OCM_VBASE (ZYNQ_ARMCORE_VBASE + ZYNQ_ARMCORE_SIZE)
#define ZYNQ_OCM_PBASE 0xfff00000
diff -r 6cccb2dc47ea -r cd1073597062 sys/arch/arm/zynq/files.zynq
--- a/sys/arch/arm/zynq/files.zynq Fri Oct 28 09:44:52 2022 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-# $NetBSD: files.zynq,v 1.2 2018/09/21 12:04:07 skrll Exp $
-#
-# Configuration info for xilinx Zynq-7000 ARM Peripherals
-#
-
-include "arch/arm/pic/files.pic"
-include "arch/arm/cortex/files.cortex"
-
-file arch/arm/zynq/zynq_space.c
-file arch/arm/zynq/zynq_dma.c
-
-file arch/arm/arm32/arm32_boot.c
-file arch/arm/arm32/arm32_kvminit.c
-file arch/arm/arm32/arm32_reboot.c
-file arch/arm/arm32/irq_dispatch.S
-
-file arch/arm/zynq/zynq7000_board.c
-
-# Console parameters
-defflag opt_zynq.h ZYNQ
-defflag opt_zynq.h ZYNQ7000
-defparam opt_zynq.h MEMSIZE
-
-# AXI bus interface and SoC domains
-device axi {[addr=-1], [size=0], [irq=-1], [irqbase=-1]} : bus_space_generic
-attach axi at mainbus
-file arch/arm/zynq/zynq_axi.c axi
-
-# System Level Control Module
-device zynqslcr
-attach zynqslcr at axi
-file arch/arm/zynq/zynq_slcr.c zynqslcr needs-flag
-
-# UART
-device zynquart
-attach zynquart at axi
-file arch/arm/zynq/zynq_uart.c zynquart needs-flag
-file arch/arm/zynq/zynq7000_uart.c zynquart
-defflag opt_zynquart.h ZYNQUARTCONSOLE
-
-# USB controller
-attach ehci at axi with zynqusb
-file arch/arm/zynq/zynq_usb.c zynqusb
-file arch/arm/zynq/zynq7000_usb.c zynqusb
-
-# SD host controller for SD/MMC
-attach sdhc at axi with sdhc_axi
-file arch/arm/zynq/zynq7000_sdhc.c sdhc_axi
-
-# Gigabit Ethernet Controller
-device cemac: ether, ifnet, arp, mii, bus_dma_generic
-attach cemac at axi
-file dev/cadence/if_cemac.c cemac
-file arch/arm/zynq/zynq_cemac.c cemac
-
diff -r 6cccb2dc47ea -r cd1073597062 sys/arch/arm/zynq/zynq7000_board.c
--- a/sys/arch/arm/zynq/zynq7000_board.c Fri Oct 28 09:44:52 2022 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,133 +0,0 @@
-/* $NetBSD: zynq7000_board.c,v 1.5 2018/10/18 09:01:53 skrll Exp $ */
-/*-
- * Copyright (c) 2015 Genetec Corporation. All rights reserved.
- * Written by Hashimoto Kenichi for Genetec Corporation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: zynq7000_board.c,v 1.5 2018/10/18 09:01:53 skrll Exp $");
-
-#include "opt_zynq.h"
-#include "arml2cc.h"
-
-#include <sys/param.h>
-#include <sys/bus.h>
-#include <sys/cpu.h>
-#include <sys/device.h>
-
-#include <arm/locore.h>
-#include <arm/cortex/a9tmr_var.h>
-#include <arm/cortex/pl310_var.h>
-#include <arm/mainbus/mainbus.h>
-
-#include <arm/zynq/zynq7000_var.h>
-#include <arm/zynq/zynq7000_reg.h>
-
-/*
- * PERIPHCLK_N is an arm root clock divider for MPcore interrupt controller.
- * PERIPHCLK_N is equal to, or greater than two.
- * see "Cortex-A9 MPCore Technical Reference Manual" -
- * Chapter 5: Clocks, Resets, and Power Management, 5.1: Clocks.
- */
-#ifndef PERIPHCLK_N
-#define PERIPHCLK_N 2
-#endif
-
-bus_space_tag_t zynq7000_ioreg_bst = &zynq_bs_tag;
-bus_space_handle_t zynq7000_ioreg_bsh;
-bus_space_tag_t zynq7000_armcore_bst = &zynq_bs_tag;
-bus_space_handle_t zynq7000_armcore_bsh;
-
-struct zynq7000_clock_info clk_info = { 0 };
-
-static void zynq7000_clock_init(struct zynq7000_clock_info *);
-
-psize_t
-zynq7000_memprobe(void)
-{
- return MEMSIZE * 1024 * 1024;
-}
-
-void
-zynq7000_bootstrap(vaddr_t iobase)
-{
- int error;
-
- zynq7000_ioreg_bsh = (bus_space_handle_t) iobase;
- error = bus_space_map(zynq7000_ioreg_bst, ZYNQ7000_IOREG_PBASE,
- ZYNQ7000_IOREG_SIZE, 0, &zynq7000_ioreg_bsh);
- if (error)
- panic("%s: failed to map Zynq %s registers: %d",
- __func__, "io", error);
-
- zynq7000_armcore_bsh = (bus_space_handle_t) iobase + ZYNQ7000_IOREG_SIZE;
- error = bus_space_map(zynq7000_armcore_bst, ZYNQ7000_ARMCORE_PBASE,
- ZYNQ7000_ARMCORE_SIZE, 0, &zynq7000_armcore_bsh);
- if (error)
- panic("%s: failed to map Zynq %s registers: %d",
- __func__, "armcore", error);
-
- struct zynq7000_clock_info * const clk = &clk_info;
- zynq7000_clock_init(clk);
-
-#if NARML2CC > 0
- arml2cc_init(zynq7000_armcore_bst, zynq7000_armcore_bsh, ARMCORE_L2C_BASE);
-#endif
-}
-
-static void
-zynq7000_clock_init(struct zynq7000_clock_info *clk)
-{
- clk->clk_ps = ZYNQ7000_PS_CLK;
-}
-
-void
-zynq7000_device_register(device_t self, void *aux)
-{
- prop_dictionary_t dict = device_properties(self);
-
- if (device_is_a(self, "armperiph")
- && device_is_a(device_parent(self), "mainbus")) {
- /*
- * XXX KLUDGE ALERT XXX
- * The iot mainbus supplies is completely wrong since it scales
- * addresses by 2. The simpliest remedy is to replace with our
- * bus space used for the armcore registers (which armperiph uses).
- */
- struct mainbus_attach_args * const mb = aux;
- mb->mb_iot = zynq7000_armcore_bst;
- return;
- }
-
- /*
- * We need to tell the A9 Global/Watchdog Timer
- * what frequency it runs at.
- */
- if (device_is_a(self, "arma9tmr") || device_is_a(self, "a9wdt")) {
- prop_dictionary_set_uint32(dict, "frequency",
- 666666666 / PERIPHCLK_N);
- return;
- }
-}
-
diff -r 6cccb2dc47ea -r cd1073597062 sys/arch/arm/zynq/zynq7000_intr.h
--- a/sys/arch/arm/zynq/zynq7000_intr.h Fri Oct 28 09:44:52 2022 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,103 +0,0 @@
-/* $NetBSD: zynq7000_intr.h,v 1.1 2015/01/23 12:34:09 hkenken Exp $ */
-/*-
- * Copyright (c) 2015 Genetec Corporation. All rights reserved.
- * Written by Hashimoto Kenichi for Genetec Corporation.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _ARM_ZYNQ_ZYNQ7000_INTR_H_
-#define _ARM_ZYNQ_ZYNQ7000_INTR_H_
-
-#define PIC_MAXSOURCES 128
-#define PIC_MAXMAXSOURCES 128
-
-/*
- * The ZYNQ7000 uses a generic interrupt controller so pull that stuff.
- */
-#include <arm/cortex/gic_intr.h>
-#include <arm/cortex/a9tmr_intr.h> /* A9 Timer PPIs */
-
-
-#define IRQ_CPU0 32
-#define IRQ_CPU1 33
-#define IRQ_L2CC 34
-#define IRQ_OCM 35
-#define IRQ__RSVD36 36
-#define IRQ_PMU0 37
-#define IRQ_PMU1 38
-#define IRQ_XADC 39
-#define IRQ_DVI 40
-#define IRQ_SWDT 41
-#define IRQ_TTC0 42
-#define IRQ__RSVD44 44
-#define IRQ_DMAC_ABORT 45
-#define IRQ_DMAC0 46
-#define IRQ_DMAC1 47
-#define IRQ_DMAC2 48
-#define IRQ_DMAC3 49
-#define IRQ_SMC 50
-#define IRQ_QSPI 51
-#define IRQ_GPIO 52
-#define IRQ_USB0 53
-#define IRQ_ETH0 54
-#define IRQ_ETH0_WU 55
-#define IRQ_SDIO0 56
-#define IRQ_I2C0 57
-#define IRQ_SPI0 58
-#define IRQ_UART0 59
-#define IRQ_CAN0 60
-#define IRQ_FPGA0 60
-#define IRQ_FPGA1 61
-#define IRQ_FPGA2 62
-#define IRQ_FPGA3 64
-#define IRQ_FPGA4 65
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