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[src/trunk]: src/sys/dev ichsmb(4): Remove confusing `lpcib_' prefix on regis...
details: https://anonhg.NetBSD.org/src/rev/b2c857379c7f
branches: trunk
changeset: 370650:b2c857379c7f
user: riastradh <riastradh%NetBSD.org@localhost>
date: Thu Sep 22 14:45:33 2022 +0000
description:
ichsmb(4): Remove confusing `lpcib_' prefix on register names.
diffstat:
sys/dev/ic/i82801lpcreg.h | 132 +++++++++++++++++++++++-----------------------
sys/dev/pci/ichsmb.c | 93 +++++++++++++++----------------
2 files changed, 111 insertions(+), 114 deletions(-)
diffs (truncated from 380 to 300 lines):
diff -r ceb133961451 -r b2c857379c7f sys/dev/ic/i82801lpcreg.h
--- a/sys/dev/ic/i82801lpcreg.h Thu Sep 22 14:45:18 2022 +0000
+++ b/sys/dev/ic/i82801lpcreg.h Thu Sep 22 14:45:33 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: i82801lpcreg.h,v 1.15 2022/09/22 14:43:04 riastradh Exp $ */
+/* $NetBSD: i82801lpcreg.h,v 1.16 2022/09/22 14:45:33 riastradh Exp $ */
/*-
* Copyright (c) 2004 The NetBSD Foundation, Inc.
@@ -166,73 +166,73 @@
*/
/* PCI configuration registers */
-#define LPCIB_SMB_BASE 0x20 /* SMBus base address */
-#define LPCIB_SMB_HOSTC 0x40 /* host configuration */
-#define LPCIB_SMB_HOSTC_HSTEN (1 << 0) /* enable host controller */
-#define LPCIB_SMB_HOSTC_SMIEN (1 << 1) /* generate SMI */
-#define LPCIB_SMB_HOSTC_I2CEN (1 << 2) /* enable I2C commands */
+#define SMB_BASE 0x20 /* SMBus base address */
+#define SMB_HOSTC 0x40 /* host configuration */
+#define SMB_HOSTC_HSTEN (1 << 0) /* enable host controller */
+#define SMB_HOSTC_SMIEN (1 << 1) /* generate SMI */
+#define SMB_HOSTC_I2CEN (1 << 2) /* enable I2C commands */
/* SMBus I/O registers */
-#define LPCIB_SMB_HS 0x00 /* host status */
-#define LPCIB_SMB_HS_BUSY (1 << 0) /* running a command */
-#define LPCIB_SMB_HS_INTR (1 << 1) /* command completed */
-#define LPCIB_SMB_HS_DEVERR (1 << 2) /* command error */
-#define LPCIB_SMB_HS_BUSERR (1 << 3) /* transaction collision */
-#define LPCIB_SMB_HS_FAILED (1 << 4) /* failed bus transaction */
-#define LPCIB_SMB_HS_SMBAL (1 << 5) /* SMBALERT# asserted */
-#define LPCIB_SMB_HS_INUSE (1 << 6) /* bus semaphore */
-#define LPCIB_SMB_HS_BDONE (1 << 7) /* byte received/transmitted */
-#define LPCIB_SMB_HS_BITS "\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED\006SMBAL\007INUSE\010BDONE"
-#define LPCIB_SMB_HC 0x02 /* host control */
-#define LPCIB_SMB_HC_INTREN (1 << 0) /* enable interrupts */
-#define LPCIB_SMB_HC_KILL (1 << 1) /* kill current transaction */
-#define LPCIB_SMB_HC_CMD_QUICK (0 << 2) /* QUICK command */
-#define LPCIB_SMB_HC_CMD_BYTE (1 << 2) /* BYTE command */
-#define LPCIB_SMB_HC_CMD_BDATA (2 << 2) /* BYTE DATA command */
-#define LPCIB_SMB_HC_CMD_WDATA (3 << 2) /* WORD DATA command */
-#define LPCIB_SMB_HC_CMD_PCALL (4 << 2) /* PROCESS CALL command */
-#define LPCIB_SMB_HC_CMD_BLOCK (5 << 2) /* BLOCK command */
-#define LPCIB_SMB_HC_CMD_I2CREAD (6 << 2) /* I2C READ command */
-#define LPCIB_SMB_HC_CMD_BLOCKP (7 << 2) /* BLOCK PROCESS command */
-#define LPCIB_SMB_HC_LASTB (1 << 5) /* last byte in block */
-#define LPCIB_SMB_HC_START (1 << 6) /* start transaction */
-#define LPCIB_SMB_HC_PECEN (1 << 7) /* enable PEC */
-#define LPCIB_SMB_HCMD 0x03 /* host command */
-#define LPCIB_SMB_TXSLVA 0x04 /* transmit slave address */
-#define LPCIB_SMB_TXSLVA_READ (1 << 0) /* read direction */
-#define LPCIB_SMB_TXSLVA_ADDR(x) (((x) & 0x7f) << 1) /* 7-bit address */
-#define LPCIB_SMB_HD0 0x05 /* host data 0 */
-#define LPCIB_SMB_HD1 0x06 /* host data 1 */
-#define LPCIB_SMB_HBDB 0x07 /* host block data byte */
-#define LPCIB_SMB_PEC 0x08 /* PEC data */
-#define LPCIB_SMB_RXSLVA 0x09 /* receive slave address */
-#define LPCIB_SMB_SD 0x0a /* receive slave data */
-#define LPCIB_SMB_SD_MSG0(x) ((x) & 0xff) /* data message byte 0 */
-#define LPCIB_SMB_SD_MSG1(x) ((x) >> 8) /* data message byte 1 */
-#define LPCIB_SMB_AS 0x0c /* auxiliary status */
-#define LPCIB_SMB_AS_CRCE (1 << 0) /* CRC error */
-#define LPCIB_SMB_AS_TCO (1 << 1) /* advanced TCO mode */
-#define LPCIB_SMB_AC 0x0d /* auxiliary control */
-#define LPCIB_SMB_AC_AAC (1 << 0) /* automatically append CRC */
-#define LPCIB_SMB_AC_E32B (1 << 1) /* enable 32-byte buffer */
-#define LPCIB_SMB_SMLPC 0x0e /* SMLink pin control */
-#define LPCIB_SMB_SMLPC_LINK0 (1 << 0) /* SMLINK0 pin state */
-#define LPCIB_SMB_SMLPC_LINK1 (1 << 1) /* SMLINK1 pin state */
-#define LPCIB_SMB_SMLPC_CLKC (1 << 2) /* SMLINK0 pin is untouched */
-#define LPCIB_SMB_SMBPC 0x0f /* SMBus pin control */
-#define LPCIB_SMB_SMBPC_CLK (1 << 0) /* SMBCLK pin state */
-#define LPCIB_SMB_SMBPC_DATA (1 << 1) /* SMBDATA pin state */
-#define LPCIB_SMB_SMBPC_CLKC (1 << 2) /* SMBCLK pin is untouched */
-#define LPCIB_SMB_SS 0x10 /* slave status */
-#define LPCIB_SMB_SS_HN (1 << 0) /* Host Notify command */
-#define LPCIB_SMB_SCMD 0x11 /* slave command */
-#define LPCIB_SMB_SCMD_INTREN (1 << 0) /* enable interrupts on HN */
-#define LPCIB_SMB_SCMD_WKEN (1 << 1) /* wake on HN */
-#define LPCIB_SMB_SCMD_SMBALDS (1 << 2) /* disable SMBALERT# intr */
-#define LPCIB_SMB_NDADDR 0x14 /* notify device address */
-#define LPCIB_SMB_NDADDR_ADDR(x) ((x) >> 1) /* 7-bit address */
-#define LPCIB_SMB_NDLOW 0x16 /* notify data low byte */
-#define LPCIB_SMB_NDHIGH 0x17 /* notify data high byte */
+#define SMB_HS 0x00 /* host status */
+#define SMB_HS_BUSY (1 << 0) /* running a command */
+#define SMB_HS_INTR (1 << 1) /* command completed */
+#define SMB_HS_DEVERR (1 << 2) /* command error */
+#define SMB_HS_BUSERR (1 << 3) /* transaction collision */
+#define SMB_HS_FAILED (1 << 4) /* failed bus transaction */
+#define SMB_HS_SMBAL (1 << 5) /* SMBALERT# asserted */
+#define SMB_HS_INUSE (1 << 6) /* bus semaphore */
+#define SMB_HS_BDONE (1 << 7) /* byte received/transmitted */
+#define SMB_HS_BITS "\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED\006SMBAL\007INUSE\010BDONE"
+#define SMB_HC 0x02 /* host control */
+#define SMB_HC_INTREN (1 << 0) /* enable interrupts */
+#define SMB_HC_KILL (1 << 1) /* kill current transaction */
+#define SMB_HC_CMD_QUICK (0 << 2) /* QUICK command */
+#define SMB_HC_CMD_BYTE (1 << 2) /* BYTE command */
+#define SMB_HC_CMD_BDATA (2 << 2) /* BYTE DATA command */
+#define SMB_HC_CMD_WDATA (3 << 2) /* WORD DATA command */
+#define SMB_HC_CMD_PCALL (4 << 2) /* PROCESS CALL command */
+#define SMB_HC_CMD_BLOCK (5 << 2) /* BLOCK command */
+#define SMB_HC_CMD_I2CREAD (6 << 2) /* I2C READ command */
+#define SMB_HC_CMD_BLOCKP (7 << 2) /* BLOCK PROCESS command */
+#define SMB_HC_LASTB (1 << 5) /* last byte in block */
+#define SMB_HC_START (1 << 6) /* start transaction */
+#define SMB_HC_PECEN (1 << 7) /* enable PEC */
+#define SMB_HCMD 0x03 /* host command */
+#define SMB_TXSLVA 0x04 /* transmit slave address */
+#define SMB_TXSLVA_READ (1 << 0) /* read direction */
+#define SMB_TXSLVA_ADDR(x) (((x) & 0x7f) << 1) /* 7-bit address */
+#define SMB_HD0 0x05 /* host data 0 */
+#define SMB_HD1 0x06 /* host data 1 */
+#define SMB_HBDB 0x07 /* host block data byte */
+#define SMB_PEC 0x08 /* PEC data */
+#define SMB_RXSLVA 0x09 /* receive slave address */
+#define SMB_SD 0x0a /* receive slave data */
+#define SMB_SD_MSG0(x) ((x) & 0xff) /* data message byte 0 */
+#define SMB_SD_MSG1(x) ((x) >> 8) /* data message byte 1 */
+#define SMB_AS 0x0c /* auxiliary status */
+#define SMB_AS_CRCE (1 << 0) /* CRC error */
+#define SMB_AS_TCO (1 << 1) /* advanced TCO mode */
+#define SMB_AC 0x0d /* auxiliary control */
+#define SMB_AC_AAC (1 << 0) /* automatically append CRC */
+#define SMB_AC_E32B (1 << 1) /* enable 32-byte buffer */
+#define SMB_SMLPC 0x0e /* SMLink pin control */
+#define SMB_SMLPC_LINK0 (1 << 0) /* SMLINK0 pin state */
+#define SMB_SMLPC_LINK1 (1 << 1) /* SMLINK1 pin state */
+#define SMB_SMLPC_CLKC (1 << 2) /* SMLINK0 pin is untouched */
+#define SMB_SMBPC 0x0f /* SMBus pin control */
+#define SMB_SMBPC_CLK (1 << 0) /* SMBCLK pin state */
+#define SMB_SMBPC_DATA (1 << 1) /* SMBDATA pin state */
+#define SMB_SMBPC_CLKC (1 << 2) /* SMBCLK pin is untouched */
+#define SMB_SS 0x10 /* slave status */
+#define SMB_SS_HN (1 << 0) /* Host Notify command */
+#define SMB_SCMD 0x11 /* slave command */
+#define SMB_SCMD_INTREN (1 << 0) /* enable interrupts on HN */
+#define SMB_SCMD_WKEN (1 << 1) /* wake on HN */
+#define SMB_SCMD_SMBALDS (1 << 2) /* disable SMBALERT# intr */
+#define SMB_NDADDR 0x14 /* notify device address */
+#define SMB_NDADDR_ADDR(x) ((x) >> 1) /* 7-bit address */
+#define SMB_NDLOW 0x16 /* notify data low byte */
+#define SMB_NDHIGH 0x17 /* notify data high byte */
/* ICH Chipset Configuration Registers (ICH6 and newer) */
#define LPCIB_RCBA 0xf0
diff -r ceb133961451 -r b2c857379c7f sys/dev/pci/ichsmb.c
--- a/sys/dev/pci/ichsmb.c Thu Sep 22 14:45:18 2022 +0000
+++ b/sys/dev/pci/ichsmb.c Thu Sep 22 14:45:33 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ichsmb.c,v 1.80 2022/09/22 14:45:18 riastradh Exp $ */
+/* $NetBSD: ichsmb.c,v 1.81 2022/09/22 14:45:33 riastradh Exp $ */
/* $OpenBSD: ichiic.c,v 1.44 2020/10/07 11:23:05 jsg Exp $ */
/*
@@ -22,7 +22,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.80 2022/09/22 14:45:18 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ichsmb.c,v 1.81 2022/09/22 14:45:33 riastradh Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -179,16 +179,16 @@
cv_init(&sc->sc_exec_wait, device_xname(self));
/* Read configuration */
- conf = pci_conf_read(pa->pa_pc, pa->pa_tag, LPCIB_SMB_HOSTC);
+ conf = pci_conf_read(pa->pa_pc, pa->pa_tag, SMB_HOSTC);
DPRINTF(("%s: conf 0x%08x\n", device_xname(sc->sc_dev), conf));
- if ((conf & LPCIB_SMB_HOSTC_HSTEN) == 0) {
+ if ((conf & SMB_HOSTC_HSTEN) == 0) {
aprint_error_dev(self, "SMBus disabled\n");
goto out;
}
/* Map I/O space */
- if (pci_mapreg_map(pa, LPCIB_SMB_BASE, PCI_MAPREG_TYPE_IO, 0,
+ if (pci_mapreg_map(pa, SMB_BASE, PCI_MAPREG_TYPE_IO, 0,
&sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size)) {
aprint_error_dev(self, "can't map I/O space\n");
goto out;
@@ -196,7 +196,7 @@
sc->sc_poll = 1;
sc->sc_ih = NULL;
- if (conf & LPCIB_SMB_HOSTC_SMIEN) {
+ if (conf & SMB_HOSTC_SMIEN) {
/* No PCI IRQ */
aprint_normal_dev(self, "interrupting at SMI\n");
} else {
@@ -308,24 +308,23 @@
mutex_enter(&sc->sc_exec_lock);
/* Clear status bits */
- bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS,
- LPCIB_SMB_HS_INTR | LPCIB_SMB_HS_DEVERR |
- LPCIB_SMB_HS_BUSERR | LPCIB_SMB_HS_FAILED);
- bus_space_barrier(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS, 1,
+ bus_space_write_1(sc->sc_iot, sc->sc_ioh, SMB_HS,
+ SMB_HS_INTR | SMB_HS_DEVERR | SMB_HS_BUSERR | SMB_HS_FAILED);
+ bus_space_barrier(sc->sc_iot, sc->sc_ioh, SMB_HS, 1,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
/* Wait for bus to be idle */
for (retries = 100; retries > 0; retries--) {
- st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HS);
- if (!(st & LPCIB_SMB_HS_BUSY))
+ st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, SMB_HS);
+ if (!(st & SMB_HS_BUSY))
break;
DELAY(ICHIIC_DELAY);
}
#ifdef ICHIIC_DEBUG
- snprintb(fbuf, sizeof(fbuf), LPCIB_SMB_HS_BITS, st);
+ snprintb(fbuf, sizeof(fbuf), SMB_HS_BITS, st);
printf("%s: exec: st %s\n", device_xname(sc->sc_dev), fbuf);
#endif
- if (st & LPCIB_SMB_HS_BUSY) {
+ if (st & SMB_HS_BUSY) {
mutex_exit(&sc->sc_exec_lock);
return (EBUSY);
}
@@ -348,58 +347,57 @@
sc->sc_i2c_xfer.done = false;
/* Set slave address and transfer direction */
- bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_TXSLVA,
- LPCIB_SMB_TXSLVA_ADDR(addr) |
- (I2C_OP_READ_P(op) ? LPCIB_SMB_TXSLVA_READ : 0));
+ bus_space_write_1(sc->sc_iot, sc->sc_ioh, SMB_TXSLVA,
+ SMB_TXSLVA_ADDR(addr) |
+ (I2C_OP_READ_P(op) ? SMB_TXSLVA_READ : 0));
b = (const uint8_t *)cmdbuf;
if (cmdlen > 0)
/* Set command byte */
- bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HCMD, b[0]);
+ bus_space_write_1(sc->sc_iot, sc->sc_ioh, SMB_HCMD, b[0]);
if (I2C_OP_WRITE_P(op)) {
/* Write data */
b = buf;
if (cmdlen == 0 && len == 1)
bus_space_write_1(sc->sc_iot, sc->sc_ioh,
- LPCIB_SMB_HCMD, b[0]);
+ SMB_HCMD, b[0]);
else if (len > 0)
bus_space_write_1(sc->sc_iot, sc->sc_ioh,
- LPCIB_SMB_HD0, b[0]);
+ SMB_HD0, b[0]);
if (len > 1)
bus_space_write_1(sc->sc_iot, sc->sc_ioh,
- LPCIB_SMB_HD1, b[1]);
+ SMB_HD1, b[1]);
}
/* Set SMBus command */
if (cmdlen == 0) {
if (len == 0)
- ctl = LPCIB_SMB_HC_CMD_QUICK;
+ ctl = SMB_HC_CMD_QUICK;
else
- ctl = LPCIB_SMB_HC_CMD_BYTE;
+ ctl = SMB_HC_CMD_BYTE;
} else if (len == 1)
- ctl = LPCIB_SMB_HC_CMD_BDATA;
+ ctl = SMB_HC_CMD_BDATA;
else if (len == 2)
- ctl = LPCIB_SMB_HC_CMD_WDATA;
+ ctl = SMB_HC_CMD_WDATA;
if ((flags & I2C_F_POLL) == 0)
- ctl |= LPCIB_SMB_HC_INTREN;
+ ctl |= SMB_HC_INTREN;
/* Start transaction */
- ctl |= LPCIB_SMB_HC_START;
- bus_space_write_1(sc->sc_iot, sc->sc_ioh, LPCIB_SMB_HC, ctl);
+ ctl |= SMB_HC_START;
+ bus_space_write_1(sc->sc_iot, sc->sc_ioh, SMB_HC, ctl);
if (flags & I2C_F_POLL) {
/* Poll for completion */
DELAY(ICHIIC_DELAY);
for (retries = 1000; retries > 0; retries--) {
- st = bus_space_read_1(sc->sc_iot, sc->sc_ioh,
- LPCIB_SMB_HS);
- if ((st & LPCIB_SMB_HS_BUSY) == 0)
+ st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, SMB_HS);
+ if ((st & SMB_HS_BUSY) == 0)
break;
DELAY(ICHIIC_DELAY);
}
- if (st & LPCIB_SMB_HS_BUSY)
+ if (st & SMB_HS_BUSY)
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