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[src/trunk]: src/sys/dev/ic tco(4): Nix PMC_TCO_BASE offset in TCO register d...



details:   https://anonhg.NetBSD.org/src/rev/da8af35a777d
branches:  trunk
changeset: 370646:da8af35a777d
user:      riastradh <riastradh%NetBSD.org@localhost>
date:      Thu Sep 22 14:43:04 2022 +0000

description:
tco(4): Nix PMC_TCO_BASE offset in TCO register definitions.

This just uses a subregion with PMC_TCO_BASE automatically applied.

No functional change intended.

diffstat:

 sys/arch/x86/pci/tco.c    |  49 +++++++++++++++++++---------------------------
 sys/dev/ic/i82801lpcreg.h |  49 +++++++++++++++++++++++-----------------------
 2 files changed, 44 insertions(+), 54 deletions(-)

diffs (177 lines):

diff -r 3e3888d46ce3 -r da8af35a777d sys/arch/x86/pci/tco.c
--- a/sys/arch/x86/pci/tco.c    Thu Sep 22 14:42:47 2022 +0000
+++ b/sys/arch/x86/pci/tco.c    Thu Sep 22 14:43:04 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: tco.c,v 1.8 2022/09/22 14:42:47 riastradh Exp $        */
+/*     $NetBSD: tco.c,v 1.9 2022/09/22 14:43:04 riastradh Exp $        */
 
 /*-
  * Copyright (c) 2015 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tco.c,v 1.8 2022/09/22 14:42:47 riastradh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tco.c,v 1.9 2022/09/22 14:43:04 riastradh Exp $");
 
 #include <sys/types.h>
 #include <sys/param.h>
@@ -259,18 +259,18 @@
                case TCO_VERSION_RCBA:
                        /* ICH6 or newer */
                        ich6period = bus_space_read_2(sc->sc_tcot, sc->sc_tcoh,
-                           PMC_TCO_TMR2 - PMC_TCO_BASE);
+                           TCO_TMR2);
                        ich6period &= 0xfc00;
                        bus_space_write_2(sc->sc_tcot, sc->sc_tcoh,
-                           PMC_TCO_TMR2 - PMC_TCO_BASE, ich6period | period);
+                           TCO_TMR2, ich6period | period);
                        break;
                case TCO_VERSION_PCIB:
                        /* ICH5 or older */
                        ich5period = bus_space_read_1(sc->sc_tcot, sc->sc_tcoh,
-                           PMC_TCO_TMR - PMC_TCO_BASE);
+                           TCO_TMR);
                        ich5period &= 0xc0;
                        bus_space_write_1(sc->sc_tcot, sc->sc_tcoh,
-                           PMC_TCO_TMR - PMC_TCO_BASE, ich5period | period);
+                           TCO_TMR, ich5period | period);
                        break;
                }
 
@@ -290,12 +290,10 @@
        /* any value is allowed */
        switch (sc->sc_version) {
        case TCO_VERSION_RCBA:
-               bus_space_write_2(sc->sc_tcot, sc->sc_tcoh,
-                   PMC_TCO_RLD - PMC_TCO_BASE, 1);
+               bus_space_write_2(sc->sc_tcot, sc->sc_tcoh, TCO_RLD, 1);
                break;
        case TCO_VERSION_PCIB:
-               bus_space_write_1(sc->sc_tcot, sc->sc_tcoh,
-                   PMC_TCO_RLD - PMC_TCO_BASE, 1);
+               bus_space_write_1(sc->sc_tcot, sc->sc_tcoh, TCO_RLD, 1);
                break;
        }
 
@@ -307,11 +305,9 @@
 {
        uint16_t ioreg;
 
-       ioreg = bus_space_read_2(sc->sc_tcot, sc->sc_tcoh,
-           PMC_TCO1_CNT - PMC_TCO_BASE);
-       ioreg |= PMC_TCO1_CNT_TCO_TMR_HLT;
-       bus_space_write_2(sc->sc_tcot, sc->sc_tcoh,
-           PMC_TCO1_CNT - PMC_TCO_BASE, ioreg);
+       ioreg = bus_space_read_2(sc->sc_tcot, sc->sc_tcoh, TCO1_CNT);
+       ioreg |= TCO1_CNT_TCO_TMR_HLT;
+       bus_space_write_2(sc->sc_tcot, sc->sc_tcoh, TCO1_CNT, ioreg);
 }
 
 static void
@@ -319,25 +315,20 @@
 {
        uint16_t ioreg;
 
-       ioreg = bus_space_read_2(sc->sc_tcot, sc->sc_tcoh,
-           PMC_TCO1_CNT - PMC_TCO_BASE);
-       ioreg &= ~PMC_TCO1_CNT_TCO_TMR_HLT;
-       bus_space_write_2(sc->sc_tcot, sc->sc_tcoh,
-           PMC_TCO1_CNT - PMC_TCO_BASE, ioreg);
+       ioreg = bus_space_read_2(sc->sc_tcot, sc->sc_tcoh, TCO1_CNT);
+       ioreg &= ~TCO1_CNT_TCO_TMR_HLT;
+       bus_space_write_2(sc->sc_tcot, sc->sc_tcoh, TCO1_CNT, ioreg);
 }
 
 static void
 tcotimer_status_reset(struct tco_softc *sc)
 {
-       bus_space_write_2(sc->sc_tcot, sc->sc_tcoh,
-           PMC_TCO1_STS - PMC_TCO_BASE,
-           PMC_TCO1_STS_TIMEOUT);
-       bus_space_write_2(sc->sc_tcot, sc->sc_tcoh,
-           PMC_TCO2_STS - PMC_TCO_BASE,
-           PMC_TCO2_STS_BOOT_STS);
-       bus_space_write_2(sc->sc_tcot, sc->sc_tcoh,
-           PMC_TCO2_STS - PMC_TCO_BASE,
-           PMC_TCO2_STS_SECONDS_TO_STS);
+       bus_space_write_2(sc->sc_tcot, sc->sc_tcoh, TCO1_STS,
+           TCO1_STS_TIMEOUT);
+       bus_space_write_2(sc->sc_tcot, sc->sc_tcoh, TCO2_STS,
+           TCO2_STS_BOOT_STS);
+       bus_space_write_2(sc->sc_tcot, sc->sc_tcoh, TCO2_STS,
+           TCO2_STS_SECONDS_TO_STS);
 }
 
 /*
diff -r 3e3888d46ce3 -r da8af35a777d sys/dev/ic/i82801lpcreg.h
--- a/sys/dev/ic/i82801lpcreg.h Thu Sep 22 14:42:47 2022 +0000
+++ b/sys/dev/ic/i82801lpcreg.h Thu Sep 22 14:43:04 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: i82801lpcreg.h,v 1.14 2022/09/22 14:42:47 riastradh Exp $      */
+/*     $NetBSD: i82801lpcreg.h,v 1.15 2022/09/22 14:43:04 riastradh Exp $      */
 
 /*-
  * Copyright (c) 2004 The NetBSD Foundation, Inc.
@@ -145,6 +145,7 @@
 #define PMC_BUS_CYC_TRACK      0x4e
 #define PMC_PM_SS_CNTL         0x50            /* SpeedStep control */
 # define PMC_PM_SS_CNTL_ARB_DIS                0x01    /* disable arbiter */
+#define PMC_TCO_BASE           0x60
 
 /*
  * General Purpose I/O Registers
@@ -253,31 +254,29 @@
 
 /*
  * System management TCO registers
- *  (offset from PMBASE)
  */
-#define PMC_TCO_BASE           0x60
-#define PMC_TCO_RLD            (PMC_TCO_BASE+0x00)
-#define PMC_TCO_TMR            (PMC_TCO_BASE+0x01)
-#define PMC_TCO_TMR2           (PMC_TCO_BASE+0x12) /* ICH6 and newer */
-# define PMC_TCO_TMR_MASK              0x3f
-#define PMC_TCO_DAT_IN         (PMC_TCO_BASE+0x02)
-#define PMC_TCO_DAT_OUT                (PMC_TCO_BASE+0x03)
-#define PMC_TCO1_STS           (PMC_TCO_BASE+0x04)
-# define PMC_TCO1_STS_TIMEOUT          0x08
-#define PMC_TCO2_STS           (PMC_TCO_BASE+0x06)
-# define PMC_TCO2_STS_BOOT_STS                 0x04
-# define PMC_TCO2_STS_SECONDS_TO_STS   0x02
-#define PMC_TCO1_CNT           (PMC_TCO_BASE+0x08)
-# define PMC_TCO1_CNT_TCO_LOCK                 (1 << 12)
-# define PMC_TCO1_CNT_TCO_TMR_HLT      (1 << 11)
-# define PMC_TCO1_CNT_SEND_NOW         (1 << 10)
-# define PMC_TCO1_CNT_NMI2SMI_EN       (1 << 9)
-# define PMC_TCO1_CNT_NMI_NOW          (1 << 8)
-#define PMC_TCO2_CNT           (PMC_TCO_BASE+0x0a)
-#define PMC_TCO_MESSAGE1       (PMC_TCO_BASE+0x0c)
-#define PMC_TCO_MESSAGE2       (PMC_TCO_BASE+0x0d)
-#define PMC_TCO_WDSTATUS       (PMC_TCO_BASE+0x0e)
-#define PMC_SW_IRQ_GEN         (PMC_TCO_BASE+0x10)
+#define TCO_RLD                        0x00
+#define TCO_TMR                        0x01 /* ICH5 and older */
+# define TCO_TMR_MASK          0x3f
+#define TCO_DAT_IN             0x02
+#define TCO_DAT_OUT            0x03
+#define TCO1_STS               0x04
+# define TCO1_STS_TIMEOUT              0x08
+#define TCO2_STS               0x06
+# define TCO2_STS_BOOT_STS             0x04
+# define TCO2_STS_SECONDS_TO_STS       0x02
+#define TCO1_CNT               0x08
+# define TCO1_CNT_TCO_LOCK             (1 << 12)
+# define TCO1_CNT_TCO_TMR_HLT          (1 << 11)
+# define TCO1_CNT_SEND_NOW             (1 << 10)
+# define TCO1_CNT_NMI2SMI_EN           (1 << 9)
+# define TCO1_CNT_NMI_NOW              (1 << 8)
+#define TCO2_CNT               0x0a
+#define TCO_MESSAGE1           0x0c
+#define TCO_MESSAGE2           0x0d
+#define TCO_WDSTATUS           0x0e
+#define TCO_SW_IRQ_GEN         0x10
+#define TCO_TMR2               0x12 /* ICH6 and newer */
 #define        TCO_REGSIZE             0x20
 
 /*



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