Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/riscv Checkpoint WIP.
details: https://anonhg.NetBSD.org/src/rev/e5d988a9c2a2
branches: trunk
changeset: 370166:e5d988a9c2a2
user: skrll <skrll%NetBSD.org@localhost>
date: Tue Sep 20 07:18:23 2022 +0000
description:
Checkpoint WIP.
QEMU RV64 virt can boot into virtual mode
OpenSBI v1.0
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|
Platform Name : riscv-virtio,qemu
Platform Features : medeleg
Platform HART Count : 1
Platform IPI Device : aclint-mswi
Platform Timer Device : aclint-mtimer @ 10000000Hz
Platform Console Device : uart8250
Platform HSM Device : ---
Platform Reboot Device : sifive_test
Platform Shutdown Device : sifive_test
Firmware Base : 0x80000000
Firmware Size : 252 KB
Runtime SBI Version : 0.3
Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*
Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I)
Domain0 Region01 : 0x0000000080000000-0x000000008003ffff ()
Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x00000000bfe00000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes
Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsuh
Boot HART Features : scounteren,mcounteren,mcountinhibit,time
Boot HART PMP Count : 16
Boot HART PMP Granularity : 4
Boot HART PMP Address Bits: 54
Boot HART MHPM Count : 16
Boot HART MIDELEG : 0x0000000000001666
Boot HART MEDELEG : 0x0000000000f0b509
------------
NetBSD start
sp: 0x0000_0000_80a0_2000
pc: 0x0000_0000_8020_0090
hart: 0x0000_0000_0000_0000
dtb: 0x0000_0000_bfe0_0000
l1: 0x0000_0000_80a0_2000
l2: 0x0000_0000_80a0_3000
uspace: 0x0000_0000_80a0_0000
bootstk: 0x0000_0000_80a0_2000
vtopdiff:0xffff_ffbf_7fe0_0000
bss: 0x0000_0000_808a_8bdc - 0x0000_0000_80a0_4000
0x0000_0000_80a0_3800: 0x0000_0000_2028_0821
kern 0x0000_0000_80a0_2000: 0x0000_0000_2008_002f
kern 0x0000_0000_80a0_2008: 0x0000_0000_2010_002f
kern 0x0000_0000_80a0_2010: 0x0000_0000_2018_002f
kern 0x0000_0000_80a0_2018: 0x0000_0000_2020_002f
kern 0x0000_0000_80a0_2020: 0x0000_0000_2028_002f
kern 0x0000_0000_80a0_2028: 0x0000_0000_2030_002f
kern 0x0000_0000_80a0_2030: 0x0000_0000_2038_002f
kern 0x0000_0000_80a0_2038: 0x0000_0000_2040_002f
kern 0x0000_0000_80a0_2040: 0x0000_0000_2048_002f
kern 0x0000_0000_80a0_2048: 0x0000_0000_2050_002f
kern 0x0000_0000_80a0_2050: 0x0000_0000_2058_002f
kern 0x0000_0000_80a0_2058: 0x0000_0000_2060_002f
kern 0x0000_0000_80a0_2060: 0x0000_0000_2068_002f
kern 0x0000_0000_80a0_2068: 0x0000_0000_2070_002f
kern 0x0000_0000_80a0_2070: 0x0000_0000_2078_002f
kern 0x0000_0000_80a0_2078: 0x0000_0000_2080_002f
dtb 0x0000_0000_80a0_2080: 0x0000_0000_2ff8_0027
PM
[ 1.0000000] FDT<0xffffffc002000000>
[ 1.0000000] consinit ok
[ 1.0000000] NetBSD/riscv (fdt) booting ...
[ 1.0000000] FDT /memory @ 0x80000000 size 0x40000000
[ 1.0000000] init_riscv: memory start 80000000 end c0000000 (len 40000000)
[ 1.0000000] bootargs: root=ld4a -v -x
[ 1.0000000] bootflag 'r' not recognised
[ 1.0000000] bootflag 'o' not recognised
[ 1.0000000] bootflag 'o' not recognised
[ 1.0000000] bootflag 't' not recognised
[ 1.0000000] bootflag '=' not recognised
[ 1.0000000] bootflag 'l' not recognised
[ 1.0000000] bootflag ' ' not recognised
[ 1.0000000] bootflag ' ' not recognised
[ 1.0000000] ------------------------------------------
[ 1.0000000] kern_vtopdiff = 0xffffffbf7fe00000
[ 1.0000000] memory_start = 0x 80000000
[ 1.0000000] memory_end = 0x c0000000
[ 1.0000000] memory_size = 0x 40000000
[ 1.0000000] kernstart_phys = 0x 80200000
[ 1.0000000] kernend_phys = 0x 80a00000
[ 1.0000000] VM_MIN_KERNEL_ADDRESS = 0xffffffc000000000
[ 1.0000000] kernstart_mega = 0xffffffc000000000
[ 1.0000000] kernstart = 0xffffffc000000000
[ 1.0000000] kernend = 0xffffffc000800000
[ 1.0000000] kernend_mega = 0xffffffc000800000
[ 1.0000000] VM_MAX_KERNEL_ADDRESS = 0xffffffd000000000
[ 1.0000000] ------------------------------------------
[ 1.0000000] panic: kernel diagnostic assertion "msgbufaddr != 0" failed: file "/home/nick/netbsd/nbcvs/src/sys/arch/riscv/riscv/riscv_machdep.c", line 564
diffstat:
sys/arch/riscv/include/locore.h | 3 +-
sys/arch/riscv/include/machdep.h | 68 ++++
sys/arch/riscv/include/pmap.h | 17 +-
sys/arch/riscv/include/vmparam.h | 13 +-
sys/arch/riscv/riscv/genassym.cf | 46 ++-
sys/arch/riscv/riscv/locore.S | 543 ++++++++++++++++++++++++++++++----
sys/arch/riscv/riscv/pmap_machdep.c | 169 +++++++++-
sys/arch/riscv/riscv/riscv_machdep.c | 246 +++++++++++++++-
8 files changed, 977 insertions(+), 128 deletions(-)
diffs (truncated from 1431 to 300 lines):
diff -r 3abd58a3ddfb -r e5d988a9c2a2 sys/arch/riscv/include/locore.h
--- a/sys/arch/riscv/include/locore.h Tue Sep 20 07:15:46 2022 +0000
+++ b/sys/arch/riscv/include/locore.h Tue Sep 20 07:18:23 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.10 2021/10/05 11:01:49 jmcneill Exp $ */
+/* $NetBSD: locore.h,v 1.11 2022/09/20 07:18:23 skrll Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -216,7 +216,6 @@
void * cpu_sendsig_getframe(struct lwp *, int, bool *);
-void init_riscv(vaddr_t, vaddr_t);
#endif
#endif /* _RISCV_LOCORE_H_ */
diff -r 3abd58a3ddfb -r e5d988a9c2a2 sys/arch/riscv/include/machdep.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/riscv/include/machdep.h Tue Sep 20 07:18:23 2022 +0000
@@ -0,0 +1,68 @@
+/* $NetBSD: machdep.h,v 1.1 2022/09/20 07:18:23 skrll Exp $ */
+
+/*-
+ * Copyright (c) 2022 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RISCV_MACHDEP_H_
+#define _RISCV_MACHDEP_H_
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: machdep.h,v 1.1 2022/09/20 07:18:23 skrll Exp $");
+
+#include <sys/proc.h>
+#include <sys/lwp.h>
+#include <sys/siginfo.h>
+
+static inline paddr_t
+riscv_kern_vtophys(vaddr_t va)
+{
+ extern unsigned long kern_vtopdiff;
+
+ return va - kern_vtopdiff;
+}
+
+static inline vaddr_t
+riscv_kern_phystov(paddr_t pa)
+{
+ extern unsigned long kern_vtopdiff;
+
+ return pa + kern_vtopdiff;
+}
+
+#define KERN_VTOPHYS(va) riscv_kern_vtophys((vaddr_t)va)
+#define KERN_PHYSTOV(pa) riscv_kern_phystov((paddr_t)pa)
+
+
+void uartputc(int);
+
+paddr_t init_mmu(paddr_t);
+void init_riscv(register_t, vaddr_t);
+
+
+#endif /* _RISCV_MACHDEP_H_ */
diff -r 3abd58a3ddfb -r e5d988a9c2a2 sys/arch/riscv/include/pmap.h
--- a/sys/arch/riscv/include/pmap.h Tue Sep 20 07:15:46 2022 +0000
+++ b/sys/arch/riscv/include/pmap.h Tue Sep 20 07:18:23 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.9 2021/05/01 07:41:24 skrll Exp $ */
+/* $NetBSD: pmap.h,v 1.10 2022/09/20 07:18:23 skrll Exp $ */
/*
* Copyright (c) 2014, 2019, 2021 The NetBSD Foundation, Inc.
@@ -117,12 +117,10 @@
#define __HAVE_PMAP_MD
struct pmap_md {
- paddr_t md_ptbr;
+ paddr_t md_ppn;
pd_entry_t *md_pdetab;
};
-void pmap_bootstrap(void);
-
struct vm_page *
pmap_md_alloc_poolpage(int flags);
vaddr_t pmap_md_map_poolpage(paddr_t, vsize_t);
@@ -132,13 +130,14 @@
paddr_t pmap_md_direct_mapped_vaddr_to_paddr(vaddr_t);
vaddr_t pmap_md_direct_map_paddr(paddr_t);
void pmap_md_init(void);
-bool pmap_md_tlb_check_entry(void *, vaddr_t, tlb_asid_t, pt_entry_t);
void pmap_md_xtab_activate(struct pmap *, struct lwp *);
void pmap_md_xtab_deactivate(struct pmap *);
void pmap_md_pdetab_init(struct pmap *);
bool pmap_md_ok_to_steal_p(const uvm_physseg_t, size_t);
+void pmap_bootstrap(vaddr_t kstart, vaddr_t kend);
+
extern vaddr_t pmap_direct_base;
extern vaddr_t pmap_direct_end;
#define PMAP_DIRECT_MAP(pa) (pmap_direct_base + (pa))
@@ -148,6 +147,14 @@
#define MEGAPAGE_ROUND(x) MEGAPAGE_TRUNC((x) + SEGOFSET)
#ifdef __PMAP_PRIVATE
+
+static inline bool
+pmap_md_tlb_check_entry(void *ctx, vaddr_t va, tlb_asid_t asid, pt_entry_t pte)
+{
+ // TLB not walked and so not called.
+ return false;
+}
+
static inline void
pmap_md_page_syncicache(struct vm_page_md *mdpg, const kcpuset_t *kc)
{
diff -r 3abd58a3ddfb -r e5d988a9c2a2 sys/arch/riscv/include/vmparam.h
--- a/sys/arch/riscv/include/vmparam.h Tue Sep 20 07:15:46 2022 +0000
+++ b/sys/arch/riscv/include/vmparam.h Tue Sep 20 07:18:23 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: vmparam.h,v 1.9 2021/05/01 07:41:24 skrll Exp $ */
+/* $NetBSD: vmparam.h,v 1.10 2022/09/20 07:18:23 skrll Exp $ */
/*-
* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
@@ -126,8 +126,15 @@
#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)-0x40000000) /* 0xffffffffc0000000 */
#endif
-#define VM_KERNEL_VM_BASE VM_MIN_KERNEL_ADDRESS
-#define VM_KERNEL_VM_SIZE 0x2000000 /* 32 MiB (8 / 16 megapages) */
+#define VM_KERNEL_BASE VM_MIN_KERNEL_ADDRESS
+#define VM_KERNEL_SIZE 0x2000000 /* 32 MiB (8 / 16 megapages) */
+#define VM_KERNEL_DTB_BASE (VM_KERNEL_BASE + VM_KERNEL_SIZE)
+#define VM_KERNEL_DTB_SIZE 0x2000000 /* 32 MiB (8 / 16 megapages) */
+
+#define VM_KERNEL_RESERVED (VM_KERNEL_SIZE + VM_KERNEL_DTB_SIZE)
+
+#define VM_KERNEL_VM_BASE (VM_MIN_KERNEL_ADDRESS + VM_KERNEL_RESERVED)
+#define VM_KERNEL_VM_SIZE (VM_MAX_KERNEL_ADDRESS - VM_KERNEL_VM_BASE)
#define VM_MAX_ADDRESS VM_MAXUSER_ADDRESS
#define VM_MAXUSER_ADDRESS32 ((vaddr_t)(1UL << 31))/* 0x0000000080000000 */
diff -r 3abd58a3ddfb -r e5d988a9c2a2 sys/arch/riscv/riscv/genassym.cf
--- a/sys/arch/riscv/riscv/genassym.cf Tue Sep 20 07:15:46 2022 +0000
+++ b/sys/arch/riscv/riscv/genassym.cf Tue Sep 20 07:18:23 2022 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: genassym.cf,v 1.11 2022/09/11 15:31:12 skrll Exp $
+# $NetBSD: genassym.cf,v 1.12 2022/09/20 07:18:23 skrll Exp $
#-
# Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -49,18 +49,13 @@
include <riscv/locore.h>
include <riscv/sysreg.h>
-#define SR_IM SR_IM
-#define SR_IM_LSHIFT __SIZEOF_LONG__ * 8 - (ilog2(SR_IM) + 1)
-#define SR_IM_RSHIFT ilog2(__LOWEST_SET_BIT(SR_IM))
-#define SR_VM SR_VM
-#define SR_U64 SR_U64
-#define SR_S64 SR_S64
-#define SR_EF SR_EF
-#define SR_PEI SR_PEI
-#define SR_EI SR_EI
-#define SR_PS SR_PS
-#define SR_S SR_S
+
+define SR_SPP SR_SPP
define SR_SIE SR_SIE
+define SR_FS SR_FS
+# define SR_PS SR_PS
+# define SR_S SR_S
+define SR_SUM SR_SUM
define CAUSE_SYSCALL CAUSE_SYSCALL
@@ -161,6 +156,7 @@
define PAGE_SIZE PAGE_SIZE
define PAGE_MASK PAGE_MASK
define PAGE_SHIFT PAGE_SHIFT
+define UPAGES UPAGES
define USRSTACK USRSTACK
ifdef __HAVE_FAST_SOFTINTS
@@ -186,6 +182,8 @@
define VM_MIN_KERNEL_ADDRESS VM_MIN_KERNEL_ADDRESS
define VM_MAX_KERNEL_ADDRESS VM_MAX_KERNEL_ADDRESS
+define VM_KERNEL_BASE VM_KERNEL_BASE
+define VM_KERNEL_SIZE VM_KERNEL_SIZE
define USPACE USPACE
ifdef XSEGSHIFT
@@ -196,6 +194,7 @@
define NPDEPG NPDEPG
define NBSEG NBSEG
+# Constants from pte.h
define PTE_D PTE_D
define PTE_A PTE_A
define PTE_G PTE_G
@@ -205,8 +204,29 @@
define PTE_R PTE_R
define PTE_V PTE_V
+define PTE_KERN PTE_KERN
+
+define L0_SHIFT L0_SHIFT
+define L1_SHIFT L1_SHIFT
+define L1_SIZE L1_SIZE
+define L1_OFFSET L1_OFFSET
+define L2_SHIFT L2_SHIFT
+define L2_SIZE L2_SIZE
+define L2_OFFSET L2_OFFSET
+#define L3_SHIFT L3_SHIFT
+#define L3_SIZE L3_SIZE
+#define L3_OFFSET L3_OFFSET
+define Ln_ENTRIES Ln_ENTRIES
+define Ln_ADDR_MASK Ln_ADDR_MASK
+#define PTE_PPN0_S PTE_PPN0_S
+#define PTE_PPN1_S PTE_PPN1_S
+#define PTE_PPN2_S PTE_PPN2_S
+#define PTE_PPN3_S PTE_PPN3_S
+#define PTE_SIZE PTE_SIZE
+define PTE_PPN_SHIFT PTE_PPN_SHIFT
+
define PM_MD_PDETAB offsetof(struct pmap, pm_md.md_pdetab)
-define PM_MD_PTBR offsetof(struct pmap, pm_md.md_ptbr)
+define PM_MD_PPN offsetof(struct pmap, pm_md.md_ppn)
# for bus_space_asm
define BS_STRIDE offsetof(struct bus_space, bs_stride)
diff -r 3abd58a3ddfb -r e5d988a9c2a2 sys/arch/riscv/riscv/locore.S
--- a/sys/arch/riscv/riscv/locore.S Tue Sep 20 07:15:46 2022 +0000
+++ b/sys/arch/riscv/riscv/locore.S Tue Sep 20 07:18:23 2022 +0000
@@ -1,11 +1,11 @@
-/* $NetBSD: locore.S,v 1.24 2022/04/10 09:50:45 andvar Exp $ */
+/* $NetBSD: locore.S,v 1.25 2022/09/20 07:18:23 skrll Exp $ */
/*-
- * Copyright (c) 2014 The NetBSD Foundation, Inc.
+ * Copyright (c) 2014, 2022 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
- * by Matt Thomas of 3am Software Foundry.
+ * by Matt Thomas of 3am Software Foundry, and by Nick Hudson.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -29,125 +29,524 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include "opt_console.h"
+#include "opt_riscv_debug.h"
+
#include <machine/asm.h>
#include "assym.h"
.globl _C_LABEL(exception_userexit)
.globl _C_LABEL(cpu_Debugger_insn)
+#if defined(VERBOSE_INIT_RISCV)
+
+#define VPRINTS(string) \
+ call locore_prints ; \
+ .asciz string ; \
+ .align 3 ; \
+
+#define VPRINTX(regno) \
+ mv a0, regno ; \
Home |
Main Index |
Thread Index |
Old Index