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[src/trunk]: src/sys/arch/powerpc/fpu Make fpu_explode() and fpu_implode() ta...
details: https://anonhg.NetBSD.org/src/rev/cbf2538315e5
branches: trunk
changeset: 369822:cbf2538315e5
user: rin <rin%NetBSD.org@localhost>
date: Fri Sep 02 12:40:49 2022 +0000
description:
Make fpu_explode() and fpu_implode() take uint64_t and uint64_t *,
instead of register number, respectively. NFC.
diffstat:
sys/arch/powerpc/fpu/fpu_emu.c | 99 ++++++++++++++++++-------------------
sys/arch/powerpc/fpu/fpu_emu.h | 6 +-
sys/arch/powerpc/fpu/fpu_explode.c | 37 +++++--------
sys/arch/powerpc/fpu/fpu_extern.h | 6 +-
sys/arch/powerpc/fpu/fpu_implode.c | 20 ++++---
5 files changed, 82 insertions(+), 86 deletions(-)
diffs (truncated from 458 to 300 lines):
diff -r 46b53e66980b -r cbf2538315e5 sys/arch/powerpc/fpu/fpu_emu.c
--- a/sys/arch/powerpc/fpu/fpu_emu.c Fri Sep 02 12:30:48 2022 +0000
+++ b/sys/arch/powerpc/fpu/fpu_emu.c Fri Sep 02 12:40:49 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: fpu_emu.c,v 1.44 2022/09/01 06:08:16 rin Exp $ */
+/* $NetBSD: fpu_emu.c,v 1.45 2022/09/02 12:40:49 rin Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -76,7 +76,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.44 2022/09/01 06:08:16 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu_emu.c,v 1.45 2022/09/02 12:40:49 rin Exp $");
#ifdef _KERNEL_OPT
#include "opt_ddb.h"
@@ -159,6 +159,7 @@
FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI \
)
+#define FR(reg) (fs->fpreg[reg])
int fpe_debug = 0;
@@ -414,8 +415,9 @@
DPRINTF(FPE_INSN,
("fpu_execute: Store SNG at %p\n",
(void *)addr));
- fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rt);
- fpu_implode(fe, fp, type, (void *)&buf);
+ fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL,
+ FR(rt));
+ fpu_implode(fe, fp, type, &buf);
if (copyout(&buf, (void *)addr, size)) {
fe->fe_addr = addr;
return (FAULT);
@@ -439,9 +441,8 @@
return (FAULT);
}
if (type != FTYPE_DBL) {
- fpu_explode(fe, fp = &fe->fe_f1, type, rt);
- fpu_implode(fe, fp, FTYPE_DBL,
- (u_int *)&fs->fpreg[rt]);
+ fpu_explode(fe, fp = &fe->fe_f1, type, FR(rt));
+ fpu_implode(fe, fp, FTYPE_DBL, &FR(rt));
}
}
if (update)
@@ -471,8 +472,8 @@
FPU_EMU_EVCNT_INCR(fcmpu);
DPRINTF(FPE_INSN, ("fpu_execute: FCMPU\n"));
rt >>= 2;
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fpu_compare(fe, 0);
/* Make sure we do the condition regs. */
cond = 0;
@@ -492,17 +493,18 @@
*/
FPU_EMU_EVCNT_INCR(frsp);
DPRINTF(FPE_INSN, ("fpu_execute: FRSP\n"));
- fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL, rb);
- fpu_implode(fe, fp, FTYPE_SNG,
- (u_int *)&fs->fpreg[rt]);
- fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt);
+ fpu_explode(fe, fp = &fe->fe_f1, FTYPE_DBL,
+ FR(rb));
+ fpu_implode(fe, fp, FTYPE_SNG, &FR(rt));
+ fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG,
+ FR(rt));
type = FTYPE_DBL | FTYPE_FPRF;
break;
case OPC63_FCTIW:
case OPC63_FCTIWZ:
FPU_EMU_EVCNT_INCR(fctiw);
DPRINTF(FPE_INSN, ("fpu_execute: FCTIW\n"));
- fpu_explode(fe, fp = &fe->fe_f1, type, rb);
+ fpu_explode(fe, fp = &fe->fe_f1, type, FR(rb));
type = FTYPE_INT;
if (instr.i_x.i_xo == OPC63_FCTIWZ)
type |= FTYPE_RD_RZ;
@@ -511,8 +513,8 @@
FPU_EMU_EVCNT_INCR(fcmpo);
DPRINTF(FPE_INSN, ("fpu_execute: FCMPO\n"));
rt >>= 2;
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fpu_compare(fe, 1);
/* Make sure we do the condition regs. */
cond = 0;
@@ -614,7 +616,7 @@
case OPC63_FCTIDZ:
FPU_EMU_EVCNT_INCR(fctid);
DPRINTF(FPE_INSN, ("fpu_execute: FCTID\n"));
- fpu_explode(fe, fp = &fe->fe_f1, type, rb);
+ fpu_explode(fe, fp = &fe->fe_f1, type, FR(rb));
type = FTYPE_LNG;
if (instr.i_x.i_xo == OPC63_FCTIDZ)
type |= FTYPE_RD_RZ;
@@ -623,7 +625,7 @@
FPU_EMU_EVCNT_INCR(fcfid);
DPRINTF(FPE_INSN, ("fpu_execute: FCFID\n"));
type = FTYPE_LNG;
- fpu_explode(fe, fp = &fe->fe_f1, type, rb);
+ fpu_explode(fe, fp = &fe->fe_f1, type, FR(rb));
type = FTYPE_DBL | FTYPE_FPRF;
break;
default:
@@ -646,28 +648,28 @@
case OPC59_FDIVS:
FPU_EMU_EVCNT_INCR(fdiv);
DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n"));
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fp = fpu_div(fe);
break;
case OPC59_FSUBS:
FPU_EMU_EVCNT_INCR(fsub);
DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n"));
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fp = fpu_sub(fe);
break;
case OPC59_FADDS:
FPU_EMU_EVCNT_INCR(fadd);
DPRINTF(FPE_INSN, ("fpu_execute: FADD\n"));
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fp = fpu_add(fe);
break;
case OPC59_FSQRTS:
FPU_EMU_EVCNT_INCR(fsqrt);
DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n"));
- fpu_explode(fe, &fe->fe_f1, type, rb);
+ fpu_explode(fe, &fe->fe_f1, type, FR(rb));
fp = fpu_sqrt(fe);
break;
case OPC63M_FSEL:
@@ -688,60 +690,56 @@
case OPC59_FRES:
FPU_EMU_EVCNT_INCR(fpres);
DPRINTF(FPE_INSN, ("fpu_execute: FPRES\n"));
- fpu_explode(fe, &fe->fe_f1, type, rb);
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fp = fpu_sqrt(fe);
- /* now we've gotta overwrite the dest reg */
- *((int *)&fe->fe_fpstate->fpreg[rt]) = 1;
- fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt);
+ fpu_explode(fe, &fe->fe_f1, FTYPE_INT, 1);
fpu_div(fe);
break;
case OPC59_FMULS:
FPU_EMU_EVCNT_INCR(fmul);
DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n"));
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rc);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rc));
fp = fpu_mul(fe);
break;
case OPC63M_FRSQRTE:
/* Reciprocal sqrt() estimate */
FPU_EMU_EVCNT_INCR(frsqrte);
DPRINTF(FPE_INSN, ("fpu_execute: FRSQRTE\n"));
- fpu_explode(fe, &fe->fe_f1, type, rb);
+ fpu_explode(fe, &fe->fe_f1, type, FR(rb));
fp = fpu_sqrt(fe);
fe->fe_f2 = *fp;
- /* now we've gotta overwrite the dest reg */
- *((int *)&fe->fe_fpstate->fpreg[rt]) = 1;
- fpu_explode(fe, &fe->fe_f1, FTYPE_INT, rt);
+ fpu_explode(fe, &fe->fe_f1, FTYPE_INT, 1);
fpu_div(fe);
break;
case OPC59_FMSUBS:
FPU_EMU_EVCNT_INCR(fmulsub);
DPRINTF(FPE_INSN, ("fpu_execute: FMULSUB\n"));
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rc);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rc));
fp = fpu_mul(fe);
fe->fe_f1 = *fp;
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fp = fpu_sub(fe);
break;
case OPC59_FMADDS:
FPU_EMU_EVCNT_INCR(fmuladd);
DPRINTF(FPE_INSN, ("fpu_execute: FMULADD\n"));
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rc);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rc));
fp = fpu_mul(fe);
fe->fe_f1 = *fp;
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fp = fpu_add(fe);
break;
case OPC59_FNMSUBS:
FPU_EMU_EVCNT_INCR(fnmsub);
DPRINTF(FPE_INSN, ("fpu_execute: FNMSUB\n"));
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rc);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rc));
fp = fpu_mul(fe);
fe->fe_f1 = *fp;
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fp = fpu_sub(fe);
/* Negate */
fp->fp_sign ^= 1;
@@ -749,11 +747,11 @@
case OPC59_FNMADDS:
FPU_EMU_EVCNT_INCR(fnmadd);
DPRINTF(FPE_INSN, ("fpu_execute: FNMADD\n"));
- fpu_explode(fe, &fe->fe_f1, type, ra);
- fpu_explode(fe, &fe->fe_f2, type, rc);
+ fpu_explode(fe, &fe->fe_f1, type, FR(ra));
+ fpu_explode(fe, &fe->fe_f2, type, FR(rc));
fp = fpu_mul(fe);
fe->fe_f1 = *fp;
- fpu_explode(fe, &fe->fe_f2, type, rb);
+ fpu_explode(fe, &fe->fe_f2, type, FR(rb));
fp = fpu_add(fe);
/* Negate */
fp->fp_sign ^= 1;
@@ -766,8 +764,9 @@
/* If the instruction was single precision, round */
if (!(instr.i_any.i_opcd & 0x4)) {
fpu_implode(fe, fp, FTYPE_SNG | FTYPE_FPRF,
- (u_int *)&fs->fpreg[rt]);
- fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG, rt);
+ &FR(rt));
+ fpu_explode(fe, fp = &fe->fe_f1, FTYPE_SNG,
+ FR(rt));
} else
type |= FTYPE_FPRF;
}
@@ -782,7 +781,7 @@
* Otherwise set new current exceptions and accrue.
*/
if (fp)
- fpu_implode(fe, fp, type, (u_int *)&fs->fpreg[rt]);
+ fpu_implode(fe, fp, type, &FR(rt));
cx = fe->fe_cx;
fsr = fe->fe_fpscr & ~(FPSCR_FEX|FPSCR_VX);
if (cx != 0) {
diff -r 46b53e66980b -r cbf2538315e5 sys/arch/powerpc/fpu/fpu_emu.h
--- a/sys/arch/powerpc/fpu/fpu_emu.h Fri Sep 02 12:30:48 2022 +0000
+++ b/sys/arch/powerpc/fpu/fpu_emu.h Fri Sep 02 12:40:49 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: fpu_emu.h,v 1.7 2022/09/01 06:08:16 rin Exp $ */
+/* $NetBSD: fpu_emu.h,v 1.8 2022/09/02 12:40:49 rin Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -185,8 +185,8 @@
*/
int fpu_shr(struct fpn *, int);
-void fpu_explode(struct fpemu *, struct fpn *, int, int);
-void fpu_implode(struct fpemu *, struct fpn *, int, u_int *);
+void fpu_explode(struct fpemu *, struct fpn *, int, uint64_t);
+void fpu_implode(struct fpemu *, struct fpn *, int, uint64_t *);
#ifdef DEBUG
#define FPE_EX 0x1
diff -r 46b53e66980b -r cbf2538315e5 sys/arch/powerpc/fpu/fpu_explode.c
--- a/sys/arch/powerpc/fpu/fpu_explode.c Fri Sep 02 12:30:48 2022 +0000
+++ b/sys/arch/powerpc/fpu/fpu_explode.c Fri Sep 02 12:40:49 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: fpu_explode.c,v 1.11 2022/09/02 12:30:48 rin Exp $ */
+/* $NetBSD: fpu_explode.c,v 1.12 2022/09/02 12:40:49 rin Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -46,7 +46,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu_explode.c,v 1.11 2022/09/02 12:30:48 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu_explode.c,v 1.12 2022/09/02 12:40:49 rin Exp $");
#include <sys/types.h>
#include <sys/systm.h>
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