[src/trunk]: src/sys/dev/ic Fix eqos(4) to work on RK3588 as well.

[ryo <ryo%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/129f60acfc2b
branches:  trunk
changeset: 369607:129f60acfc2b
user:      ryo <ryo%NetBSD.org@localhost>
date:      Tue Aug 23 05:41:46 2022 +0000

description:
Fix eqos(4) to work on RK3588 as well.

- Several registers needed to be initialized
- Add some register definitions

diffstat:

 sys/dev/ic/dwc_eqos.c     |  28 +++++++++++++++++++++++++---
 sys/dev/ic/dwc_eqos_reg.h |  12 +++++++++++-
 2 files changed, 36 insertions(+), 4 deletions(-)

diffs (112 lines):

diff -r e2bad4ba3f93 -r 129f60acfc2b sys/dev/ic/dwc_eqos.c
--- a/sys/dev/ic/dwc_eqos.c     Tue Aug 23 05:40:46 2022 +0000
+++ b/sys/dev/ic/dwc_eqos.c     Tue Aug 23 05:41:46 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_eqos.c,v 1.9 2022/08/06 17:53:49 martin Exp $ */
+/* $NetBSD: dwc_eqos.c,v 1.10 2022/08/23 05:41:46 ryo Exp $ */
 
 /*-
  * Copyright (c) 2022 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -33,7 +33,7 @@
 #include "opt_net_mpsafe.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: dwc_eqos.c,v 1.9 2022/08/06 17:53:49 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dwc_eqos.c,v 1.10 2022/08/23 05:41:46 ryo Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -552,7 +552,7 @@
 {
        struct ifnet *ifp = &sc->sc_ec.ec_if;
        struct mii_data *mii = &sc->sc_mii;
-       uint32_t val;
+       uint32_t val, tqs, rqs;
 
        EQOS_ASSERT_LOCKED(sc);
        EQOS_ASSERT_TXLOCKED(sc);
@@ -599,6 +599,24 @@
            GMAC_MTL_RXQ0_OPERATION_MODE_FEP |
            GMAC_MTL_RXQ0_OPERATION_MODE_FUP);
 
+       /*
+        * TX/RX fifo size in hw_feature[1] are log2(n/128), and
+        * TQS/RQS in TXQ0/RXQ0_OPERATION_MODE are n/256-1.
+        */
+       tqs = (128 << __SHIFTOUT(sc->sc_hw_feature[1],
+           GMAC_MAC_HW_FEATURE1_TXFIFOSIZE) / 256) - 1;
+       val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE);
+       val &= ~GMAC_MTL_TXQ0_OPERATION_MODE_TQS;
+       val |= __SHIFTIN(tqs, GMAC_MTL_TXQ0_OPERATION_MODE_TQS);
+       WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, val);
+
+       rqs = (128 << __SHIFTOUT(sc->sc_hw_feature[1],
+           GMAC_MAC_HW_FEATURE1_RXFIFOSIZE) / 256) - 1;
+       val = RD4(sc, GMAC_MTL_RXQ0_OPERATION_MODE);
+       val &= ~GMAC_MTL_RXQ0_OPERATION_MODE_RQS;
+       val |= __SHIFTIN(rqs, GMAC_MTL_RXQ0_OPERATION_MODE_RQS);
+       WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE, val);
+
        /* Enable flow control */
        val = RD4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL);
        val |= 0xFFFFU << GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT;
@@ -608,6 +626,10 @@
        val |= GMAC_MAC_RX_FLOW_CTRL_RFE;
        WR4(sc, GMAC_MAC_RX_FLOW_CTRL, val);
 
+       /* set RX queue mode. must be in DCB mode. */
+       val = __SHIFTIN(GMAC_RXQ_CTRL0_EN_DCB, GMAC_RXQ_CTRL0_EN_MASK);
+       WR4(sc, GMAC_RXQ_CTRL0, val);
+
        /* Enable transmitter and receiver */
        val = RD4(sc, GMAC_MAC_CONFIGURATION);
        val |= GMAC_MAC_CONFIGURATION_BE;
diff -r e2bad4ba3f93 -r 129f60acfc2b sys/dev/ic/dwc_eqos_reg.h
--- a/sys/dev/ic/dwc_eqos_reg.h Tue Aug 23 05:40:46 2022 +0000
+++ b/sys/dev/ic/dwc_eqos_reg.h Tue Aug 23 05:41:46 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dwc_eqos_reg.h,v 1.4 2022/03/17 05:45:23 mrg Exp $ */
+/* $NetBSD: dwc_eqos_reg.h,v 1.5 2022/08/23 05:41:46 ryo Exp $ */
 
 /*-
  * Copyright (c) 2022 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -66,8 +66,10 @@
 #define         GMAC_MAC_RX_FLOW_CTRL_RFE              (1U << 0)
 #define        GMAC_RXQ_CTRL0                          0x00A0
 #define         GMAC_RXQ_CTRL0_EN_MASK                 0x3
+#define         GMAC_RXQ_CTRL0_EN_AVB                  0x1
 #define         GMAC_RXQ_CTRL0_EN_DCB                  0x2
 #define        GMAC_RXQ_CTRL1                          0x00A4
+#define        GMAC_RXQ_CTRL2                          0x00A8
 #define        GMAC_MAC_INTERRUPT_STATUS               0x00B0
 #define        GMAC_MAC_INTERRUPT_ENABLE               0x00B4
 #define        GMAC_MAC_RX_TX_STATUS                   0x00B8
@@ -91,6 +93,8 @@
 #define         GMAC_MAC_VERSION_SNPSVER_MASK          0xFFU
 #define        GMAC_MAC_DEBUG                          0x0114
 #define        GMAC_MAC_HW_FEATURE(n)                  (0x011C + 0x4 * (n))
+#define         GMAC_MAC_HW_FEATURE1_TXFIFOSIZE        __BITS(10,6)
+#define         GMAC_MAC_HW_FEATURE1_RXFIFOSIZE        __BITS(5,0)
 #define         GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT      14
 #define         GMAC_MAC_HW_FEATURE1_ADDR64_MASK       (0x3U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT)
 #define         GMAC_MAC_HW_FEATURE1_ADDR64_32BIT      (0x0U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT)
@@ -196,6 +200,8 @@
 #define         GMAC_MTL_INTERRUPT_STATUS_DBGIS        (1U << 17)
 #define         GMAC_MTL_INTERRUPT_STATUS_Q0IS         (1U << 0)
 #define        GMAC_MTL_TXQ0_OPERATION_MODE            0x0D00
+#define         GMAC_MTL_TXQ0_OPERATION_MODE_TQS               __BITS(24,16)
+#define         GMAC_MTL_TXQ0_OPERATION_MODE_TTC               __BITS(6,4)
 #define         GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT       2
 #define         GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK        (0x3U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)
 #define         GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_EN          (2U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)
@@ -209,6 +215,10 @@
 #define         GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE        (1U << 8)
 #define         GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS      (1U << 0)
 #define        GMAC_MTL_RXQ0_OPERATION_MODE            0x0D30
+#define  GMAC_MTL_RXQ0_OPERATION_MODE_RQS              __BITS(29,20)
+#define  GMAC_MTL_RXQ0_OPERATION_MODE_RFD              __BITS(19,14)
+#define  GMAC_MTL_RXQ0_OPERATION_MODE_RFA              __BITS(13,8)
+#define         GMAC_MTL_RXQ0_OPERATION_MODE_EHFC              (1U << 7)
 #define         GMAC_MTL_RXQ0_OPERATION_MODE_RSF               (1U << 5)
 #define         GMAC_MTL_RXQ0_OPERATION_MODE_FEP               (1U << 4)
 #define         GMAC_MTL_RXQ0_OPERATION_MODE_FUP               (1U << 3)