[src/trunk]: src/sys/dev/pci Add three new extended capabilities:

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/8f59cbbc6c48
branches:  trunk
changeset: 359917:8f59cbbc6c48
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Mon Jan 31 10:11:33 2022 +0000

description:
Add three new extended capabilities:

  - Physical Layer 32.0 GT/s
  - Alternate Protocol
  - System Firmware Intermediary

diffstat:

 sys/dev/pci/pci_subr.c |  10 ++++++++--
 sys/dev/pci/pcireg.h   |   5 ++++-
 2 files changed, 12 insertions(+), 3 deletions(-)

diffs (50 lines):

diff -r b7f826c98b25 -r 8f59cbbc6c48 sys/dev/pci/pci_subr.c
--- a/sys/dev/pci/pci_subr.c    Mon Jan 31 09:16:09 2022 +0000
+++ b/sys/dev/pci/pci_subr.c    Mon Jan 31 10:11:33 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pci_subr.c,v 1.239 2022/01/08 12:59:34 tnn Exp $       */
+/*     $NetBSD: pci_subr.c,v 1.240 2022/01/31 10:11:33 msaitoh Exp $   */
 
 /*
  * Copyright (c) 1997 Zubin D. Dittia.  All rights reserved.
@@ -40,7 +40,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.239 2022/01/08 12:59:34 tnn Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pci_subr.c,v 1.240 2022/01/31 10:11:33 msaitoh Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_pci.h"
@@ -4572,6 +4572,12 @@
          NULL },
        { PCI_EXTCAP_NPEM,      "Native PCIe Enclosure Management",
          NULL },
+       { PCI_EXTCAP_PL32G,     "Physical Layer 32.0 GT/s",
+         NULL },
+       { PCI_EXTCAP_AP,        "Alternate Protocol",
+         NULL },
+       { PCI_EXTCAP_SFI,       "System Firmware Intermediary",
+         NULL },
 };
 
 static int
diff -r b7f826c98b25 -r 8f59cbbc6c48 sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h      Mon Jan 31 09:16:09 2022 +0000
+++ b/sys/dev/pci/pcireg.h      Mon Jan 31 10:11:33 2022 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pcireg.h,v 1.163 2022/01/01 03:27:53 msaitoh Exp $     */
+/*     $NetBSD: pcireg.h,v 1.164 2022/01/31 10:11:33 msaitoh Exp $     */
 
 /*
  * Copyright (c) 1995, 1996, 1999, 2000
@@ -1571,6 +1571,9 @@
 #define        PCI_EXTCAP_LMR          0x0027  /* Lane Margining at the Receiver */
 #define        PCI_EXTCAP_HIERARCHYID  0x0028  /* Hierarchy ID */
 #define        PCI_EXTCAP_NPEM         0x0029  /* Native PCIe Enclosure Management */
+#define        PCI_EXTCAP_PL32G        0x002a  /* Physical Layer 32.0 GT/s */
+#define        PCI_EXTCAP_AP           0x002b  /* Alternate Protocol */
+#define        PCI_EXTCAP_SFI          0x002c  /* System Firmware Intermediary */
 
 /*
  * Extended capability ID: 0x0001