Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src/sys/arch/x86/include Whitespace. No functional change.
details: https://anonhg.NetBSD.org/src/rev/dd8186bd5388
branches: trunk
changeset: 359640:dd8186bd5388
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Sat Jan 15 10:09:15 2022 +0000
description:
Whitespace. No functional change.
diffstat:
sys/arch/x86/include/specialreg.h | 44 +++++++++++++++++++-------------------
1 files changed, 22 insertions(+), 22 deletions(-)
diffs (59 lines):
diff -r 001368b6c2ef -r dd8186bd5388 sys/arch/x86/include/specialreg.h
--- a/sys/arch/x86/include/specialreg.h Sat Jan 15 09:58:23 2022 +0000
+++ b/sys/arch/x86/include/specialreg.h Sat Jan 15 10:09:15 2022 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: specialreg.h,v 1.184 2022/01/15 09:58:23 msaitoh Exp $ */
+/* $NetBSD: specialreg.h,v 1.185 2022/01/15 10:09:15 msaitoh Exp $ */
/*
* Copyright (c) 2014-2020 The NetBSD Foundation, Inc.
@@ -781,28 +781,28 @@
*/
/* %ebx */
-#define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */
-#define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */
-#define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */
-#define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */
-#define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */
-#define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */
-#define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */
-#define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */
-#define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */
-#define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */
-#define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */
-#define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */
-#define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */
-#define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */
-#define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */
+#define CPUID_CAPEX_CLZERO __BIT(0) /* CLZERO instruction */
+#define CPUID_CAPEX_IRPERF __BIT(1) /* InstRetCntMsr */
+#define CPUID_CAPEX_XSAVEERPTR __BIT(2) /* RstrFpErrPtrs by XRSTOR */
+#define CPUID_CAPEX_RDPRU __BIT(4) /* RDPRU instruction */
+#define CPUID_CAPEX_MCOMMIT __BIT(8) /* MCOMMIT instruction */
+#define CPUID_CAPEX_WBNOINVD __BIT(9) /* WBNOINVD instruction */
+#define CPUID_CAPEX_IBPB __BIT(12) /* Speculation Control IBPB */
+#define CPUID_CAPEX_IBRS __BIT(14) /* Speculation Control IBRS */
+#define CPUID_CAPEX_STIBP __BIT(15) /* Speculation Control STIBP */
+#define CPUID_CAPEX_IBRS_ALWAYSON __BIT(16) /* IBRS always on mode */
+#define CPUID_CAPEX_STIBP_ALWAYSON __BIT(17) /* STIBP always on mode */
+#define CPUID_CAPEX_PREFER_IBRS __BIT(18) /* IBRS preferred */
+#define CPUID_CAPEX_SSBD __BIT(24) /* Speculation Control SSBD */
+#define CPUID_CAPEX_VIRT_SSBD __BIT(25) /* Virt Spec Control SSBD */
+#define CPUID_CAPEX_SSB_NO __BIT(26) /* SSBD not required */
-#define CPUID_CAPEX_FLAGS "\20" \
- "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \
- "\5RDPRU" "\7B6" \
- "\11MCOMMIT" "\12WBNOINVD" "\13B10" \
- "\15IBPB" "\16B13" "\17IBRS" "\20STIBP" \
- "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \
+#define CPUID_CAPEX_FLAGS "\20" \
+ "\1CLZERO" "\2IRPERF" "\3XSAVEERPTR" \
+ "\5RDPRU" "\7B6" \
+ "\11MCOMMIT" "\12WBNOINVD" "\13B10" \
+ "\15IBPB" "\16B13" "\17IBRS" "\20STIBP" \
+ "\21IBRS_ALWAYSON" "\22STIBP_ALWAYSON" "\23PREFER_IBRS" "\24B19" \
"\31SSBD" "\32VIRT_SSBD" "\33SSB_NO"
/* %ecx */
Home |
Main Index |
Thread Index |
Old Index