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[src/netbsd-9]: src/usr.sbin/cpuctl/arch Pull up the following (all via patch...
details: https://anonhg.NetBSD.org/src/rev/ff35bb47ece6
branches: netbsd-9
changeset: 1029166:ff35bb47ece6
user: martin <martin%NetBSD.org@localhost>
date: Fri Dec 24 12:58:14 2021 +0000
description:
Pull up the following (all via patch), requested by msaitoh in ticket #1396:
usr.sbin/cpuctl/arch/i386.c 1.118-1.119, 1.121-1.122
usr.sbin/cpuctl/arch/cpuctl_i386.h 1.6
sys/arch/x86/x86/identcpu_subr.c 1.8-1.9
sys/arch/x86/x86/identcpu.c 1.123
sys/arch/x86/include/cacheinfo.h 1.30
sys/arch/x86/include/cpu.h 1.132
- Fix a bug that some TLB related lines were not printed.
- Fix a bug that STLB is printed as DTLB.
- If a TLB is variable sized, print the max size instead of error message.
- Cosmetic changes to improve readability.
diffstat:
sys/arch/x86/include/cacheinfo.h | 35 ++--
sys/arch/x86/include/cpu.h | 3 +-
sys/arch/x86/x86/identcpu.c | 83 +-----------
sys/arch/x86/x86/identcpu_subr.c | 81 +++++++++++-
usr.sbin/cpuctl/arch/cpuctl_i386.h | 3 +-
usr.sbin/cpuctl/arch/i386.c | 261 ++++++++++++------------------------
6 files changed, 192 insertions(+), 274 deletions(-)
diffs (truncated from 779 to 300 lines):
diff -r 5efc083cf89b -r ff35bb47ece6 sys/arch/x86/include/cacheinfo.h
--- a/sys/arch/x86/include/cacheinfo.h Sun Dec 19 16:39:28 2021 +0000
+++ b/sys/arch/x86/include/cacheinfo.h Fri Dec 24 12:58:14 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cacheinfo.h,v 1.28 2019/07/26 10:03:40 msaitoh Exp $ */
+/* $NetBSD: cacheinfo.h,v 1.28.2.1 2021/12/24 12:58:14 martin Exp $ */
#ifndef _X86_CACHEINFO_H_
#define _X86_CACHEINFO_H_
@@ -222,39 +222,39 @@
__CI_TBL(CAI_DTLB2, 0x05, 4, 32, 4 * 1024 * 1024, NULL), \
__CI_TBL(CAI_ITLB2, 0x0b, 4, 4, 4 * 1024 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0x4f, 0xff, 32, 4 * 1024, NULL), \
-__CI_TBL(CAI_ITLB, 0x50, 0xff, 64, 4 * 1024, "4K/4M: 64 entries"), \
-__CI_TBL(CAI_ITLB, 0x51, 0xff, 64, 4 * 1024, "4K/4M: 128 entries"),\
-__CI_TBL(CAI_ITLB, 0x52, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\
-__CI_TBL(CAI_ITLB2, 0x55, 0xff, 64, 4 * 1024, "2M/4M: 7 entries"), \
+__CI_TBL(CAI_ITLB, 0x50, 0xff, 64, 4 * 1024, "64 4K/4M entries"), \
+__CI_TBL(CAI_ITLB, 0x51, 0xff, 64, 4 * 1024, "128 4K/4M entries"),\
+__CI_TBL(CAI_ITLB, 0x52, 0xff, 64, 4 * 1024, "256 4K/4M entries"),\
+__CI_TBL(CAI_ITLB2, 0x55, 0xff, 64, 4 * 1024, "7 2M/4M entries"), \
__CI_TBL(CAI_DTLB2, 0x56, 4, 16, 4 * 1024 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0x57, 4, 16, 4 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0x59, 0xff, 16, 4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB2, 0x5a, 0xff, 64, 4 * 1024, "2M/4M: 32 entries (L0)"), \
-__CI_TBL(CAI_DTLB, 0x5b, 0xff, 64, 4 * 1024, "4K/4M: 64 entries"), \
-__CI_TBL(CAI_DTLB, 0x5c, 0xff, 64, 4 * 1024, "4K/4M: 128 entries"),\
-__CI_TBL(CAI_DTLB, 0x5d, 0xff, 64, 4 * 1024, "4K/4M: 256 entries"),\
+__CI_TBL(CAI_DTLB2, 0x5a, 0xff, 64, 4 * 1024, "32 2M/4M entries (L0)"), \
+__CI_TBL(CAI_DTLB, 0x5b, 0xff, 64, 4 * 1024, "64 4K/4M entries"), \
+__CI_TBL(CAI_DTLB, 0x5c, 0xff, 64, 4 * 1024, "128 4K/4M entries"),\
+__CI_TBL(CAI_DTLB, 0x5d, 0xff, 64, 4 * 1024, "256 4K/4M entries"),\
__CI_TBL(CAI_ITLB, 0x61, 0xff, 48, 4 * 1024, NULL), \
__CI_TBL(CAI_L1_1GBDTLB,0x63, 4, 4,1024*1024 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0x64, 4,512, 4 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0x6a, 8, 64, 4 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0x6b, 8,256, 4 * 1024, NULL), \
-__CI_TBL(CAI_L2_DTLB2, 0x6c, 8,128, 0, "2M/4M: 128 entries"),\
+__CI_TBL(CAI_L2_DTLB2, 0x6c, 8,128, 0, "128 2M/4M entries"),\
__CI_TBL(CAI_L1_1GBDTLB,0x6d,0xff, 16,1024*1024 * 1024, NULL), \
-__CI_TBL(CAI_ITLB2, 0x76, 0xff, 8, 4 * 1024 * 1024, "2M/4M: 8 entries"), \
+__CI_TBL(CAI_ITLB2, 0x76, 0xff, 8, 4 * 1024 * 1024, "8 2M/4M entries"), \
__CI_TBL(CAI_DTLB, 0xa0, 0xff, 32, 4 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0xb0, 4,128, 4 * 1024, NULL), \
-__CI_TBL(CAI_ITLB2, 0xb1, 4, 64, 0, "8 2M/4 4M entries"), \
+__CI_TBL(CAI_ITLB2, 0xb1, 4, 64, 0, "8 2M & 4 4M entries"), \
__CI_TBL(CAI_ITLB, 0xb2, 4, 64, 4 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0xb3, 4,128, 4 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0xb4, 4,256, 4 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0xb5, 8, 64, 4 * 1024, NULL), \
__CI_TBL(CAI_ITLB, 0xb6, 8,128, 4 * 1024, NULL), \
__CI_TBL(CAI_DTLB, 0xba, 4, 64, 4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB2, 0xc0, 4, 8, 4 * 1024, "4K/4M: 8 entries"), \
-__CI_TBL(CAI_L2_STLB2, 0xc1, 8,1024, 4 * 1024, "4K/2M: 1024 entries"), \
-__CI_TBL(CAI_DTLB2, 0xc2, 4, 16, 4 * 1024, "4K/2M: 16 entries"), \
+__CI_TBL(CAI_DTLB2, 0xc0, 4, 8, 4 * 1024, "8 4K/4M entries"), \
+__CI_TBL(CAI_L2_STLB2, 0xc1, 8,1024, 4 * 1024, "1024 4K/2M entries"), \
+__CI_TBL(CAI_DTLB2, 0xc2, 4, 16, 4 * 1024, "16 4K/2M entries"), \
__CI_TBL(CAI_L2_STLB, 0xc3, 6,1536, 4 * 1024, NULL), \
-__CI_TBL(CAI_DTLB2, 0xc4, 4, 32, 4 * 1024, "2M/4M: 32 entries"), \
+__CI_TBL(CAI_DTLB2, 0xc4, 4, 32, 4 * 1024, "32 2M/4M entries"), \
__CI_TBL(CAI_L2_STLB, 0xca, 4,512, 4 * 1024, NULL), \
__CI_TBL(CAI_ICACHE, 0x06, 4, 8 * 1024, 32, NULL), \
__CI_TBL(CAI_ICACHE, 0x08, 4, 16 * 1024, 32, NULL), \
@@ -357,4 +357,7 @@
__CI_TBL(0, 0x00, 0, 0, 0, NULL) \
}
+const struct x86_cache_info *cpu_cacheinfo_lookup(
+ const struct x86_cache_info *, uint8_t);
+
#endif /* _X86_CACHEINFO_H_ */
diff -r 5efc083cf89b -r ff35bb47ece6 sys/arch/x86/include/cpu.h
--- a/sys/arch/x86/include/cpu.h Sun Dec 19 16:39:28 2021 +0000
+++ b/sys/arch/x86/include/cpu.h Fri Dec 24 12:58:14 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.107.2.1 2020/07/15 17:25:08 martin Exp $ */
+/* $NetBSD: cpu.h,v 1.107.2.2 2021/12/24 12:58:14 martin Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
@@ -485,6 +485,7 @@
/* identcpu_subr.c */
uint64_t cpu_tsc_freq_cpuid(struct cpu_info *);
+void cpu_dcp_cacheinfo(struct cpu_info *, uint32_t);
typedef enum vm_guest {
VM_GUEST_NO = 0,
diff -r 5efc083cf89b -r ff35bb47ece6 sys/arch/x86/x86/identcpu.c
--- a/sys/arch/x86/x86/identcpu.c Sun Dec 19 16:39:28 2021 +0000
+++ b/sys/arch/x86/x86/identcpu.c Fri Dec 24 12:58:14 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: identcpu.c,v 1.93.2.4 2021/12/08 15:44:16 martin Exp $ */
+/* $NetBSD: identcpu.c,v 1.93.2.5 2021/12/24 12:58:14 martin Exp $ */
/*-
* Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.93.2.4 2021/12/08 15:44:16 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.93.2.5 2021/12/24 12:58:14 martin Exp $");
#include "opt_xen.h"
@@ -93,79 +93,6 @@
"Vortex86"
};
-static const struct x86_cache_info *
-cache_info_lookup(const struct x86_cache_info *cai, uint8_t desc)
-{
- int i;
-
- for (i = 0; cai[i].cai_desc != 0; i++) {
- if (cai[i].cai_desc == desc)
- return (&cai[i]);
- }
-
- return (NULL);
-}
-
-/*
- * Get cache info from one of the following:
- * Intel Deterministic Cache Parameter Leaf (0x04)
- * AMD Cache Topology Information Leaf (0x8000001d)
- */
-static void
-cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf)
-{
- u_int descs[4];
- int type, level, ways, partitions, linesize, sets, totalsize;
- int caitype = -1;
- int i;
-
- for (i = 0; ; i++) {
- x86_cpuid2(leaf, i, descs);
- type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
- if (type == CPUID_DCP_CACHETYPE_N)
- break;
- level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
- switch (level) {
- case 1:
- if (type == CPUID_DCP_CACHETYPE_I)
- caitype = CAI_ICACHE;
- else if (type == CPUID_DCP_CACHETYPE_D)
- caitype = CAI_DCACHE;
- else
- caitype = -1;
- break;
- case 2:
- if (type == CPUID_DCP_CACHETYPE_U)
- caitype = CAI_L2CACHE;
- else
- caitype = -1;
- break;
- case 3:
- if (type == CPUID_DCP_CACHETYPE_U)
- caitype = CAI_L3CACHE;
- else
- caitype = -1;
- break;
- default:
- caitype = -1;
- break;
- }
- if (caitype == -1)
- continue;
-
- ways = __SHIFTOUT(descs[1], CPUID_DCP_WAYS) + 1;
- partitions =__SHIFTOUT(descs[1], CPUID_DCP_PARTITIONS)
- + 1;
- linesize = __SHIFTOUT(descs[1], CPUID_DCP_LINESIZE)
- + 1;
- sets = descs[2] + 1;
- totalsize = ways * partitions * linesize * sets;
- ci->ci_cinfo[caitype].cai_totalsize = totalsize;
- ci->ci_cinfo[caitype].cai_associativity = ways;
- ci->ci_cinfo[caitype].cai_linesize = linesize;
- }
-}
-
static void
cpu_probe_intel_cache(struct cpu_info *ci)
{
@@ -188,7 +115,7 @@
desc = (descs[i] >> (j * 8)) & 0xff;
if (desc == 0)
continue;
- cai = cache_info_lookup(
+ cai = cpu_cacheinfo_lookup(
intel_cpuid_cache_info, desc);
if (cai != NULL) {
ci->ci_cinfo[cai->cai_index] =
@@ -305,7 +232,7 @@
cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]);
cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
@@ -321,7 +248,7 @@
cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]);
cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]);
- cp = cache_info_lookup(amd_cpuid_l2l3cache_assoc_info,
+ cp = cpu_cacheinfo_lookup(amd_cpuid_l2l3cache_assoc_info,
cai->cai_associativity);
if (cp != NULL)
cai->cai_associativity = cp->cai_associativity;
diff -r 5efc083cf89b -r ff35bb47ece6 sys/arch/x86/x86/identcpu_subr.c
--- a/sys/arch/x86/x86/identcpu_subr.c Sun Dec 19 16:39:28 2021 +0000
+++ b/sys/arch/x86/x86/identcpu_subr.c Fri Dec 24 12:58:14 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: identcpu_subr.c,v 1.7.2.2 2020/07/10 11:20:29 martin Exp $ */
+/* $NetBSD: identcpu_subr.c,v 1.7.2.3 2021/12/24 12:58:14 martin Exp $ */
/*-
* Copyright (c) 2020 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
* See src/usr.sbin/cpuctl/{Makefile, arch/i386.c}).
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu_subr.c,v 1.7.2.2 2020/07/10 11:20:29 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu_subr.c,v 1.7.2.3 2021/12/24 12:58:14 martin Exp $");
#ifdef _KERNEL_OPT
#include "lapic.h"
@@ -47,6 +47,7 @@
#include <sys/systm.h>
#include <x86/cpuvar.h>
#include <x86/apicvar.h>
+#include <x86/cacheinfo.h>
#include <machine/cpufunc.h>
#include <machine/cputypes.h>
#include <machine/specialreg.h>
@@ -56,6 +57,7 @@
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
+#include <x86/cacheinfo.h>
#include "cpuctl.h"
#include "cpuctl_i386.h"
#endif
@@ -69,7 +71,7 @@
if (!((ci->ci_max_cpuid >= 0x15) && (cpu_vendor == CPUVENDOR_INTEL)))
return 0;
-
+
x86_cpuid(0x15, descs);
denominator = descs[0];
numerator = descs[1];
@@ -143,3 +145,76 @@
return freq;
}
+
+const struct x86_cache_info *
+cpu_cacheinfo_lookup(const struct x86_cache_info *cai, uint8_t desc)
+{
+ int i;
+
+ for (i = 0; cai[i].cai_desc != 0; i++) {
+ if (cai[i].cai_desc == desc)
+ return &cai[i];
+ }
+
+ return NULL;
+}
+
+/*
+ * Get cache info from one of the following:
+ * Intel Deterministic Cache Parameter Leaf (0x04)
+ * AMD Cache Topology Information Leaf (0x8000001d)
+ */
+void
+cpu_dcp_cacheinfo(struct cpu_info *ci, uint32_t leaf)
+{
+ u_int descs[4];
+ int type, level, ways, partitions, linesize, sets, totalsize;
+ int caitype = -1;
+ int i;
+
+ for (i = 0; ; i++) {
+ x86_cpuid2(leaf, i, descs);
+ type = __SHIFTOUT(descs[0], CPUID_DCP_CACHETYPE);
+ if (type == CPUID_DCP_CACHETYPE_N)
+ break;
+ level = __SHIFTOUT(descs[0], CPUID_DCP_CACHELEVEL);
+ switch (level) {
+ case 1:
+ if (type == CPUID_DCP_CACHETYPE_I)
+ caitype = CAI_ICACHE;
+ else if (type == CPUID_DCP_CACHETYPE_D)
+ caitype = CAI_DCACHE;
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