Source-Changes-HG archive
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index][Old Index]
[src/trunk]: src s/endianess/endianness/
details: https://anonhg.NetBSD.org/src/rev/04c7ebb0df59
branches: trunk
changeset: 1025531:04c7ebb0df59
user: msaitoh <msaitoh%NetBSD.org@localhost>
date: Wed Nov 10 17:19:29 2021 +0000
description:
s/endianess/endianness/
diffstat:
sbin/dkscan_bsdlabel/dkscan_bsdlabel.8 | 4 ++--
sys/arch/mips/atheros/dev/ohci_arbus.c | 6 +++---
sys/arch/mips/cavium/dev/octeon_xhci.c | 4 ++--
sys/arch/mips/rmi/rmixl_ohci.c | 6 +++---
sys/arch/newsmips/apbus/if_snvar.h | 4 ++--
sys/arch/sgimips/dev/crimereg.h | 4 ++--
sys/dev/ic/ahcisata_core.c | 6 +++---
sys/dev/ic/dm9000.c | 6 +++---
sys/dev/ic/i82596.c | 6 +++---
sys/dev/ic/mpt.h | 4 ++--
sys/dev/ic/nvmeio.h | 4 ++--
sys/dev/ic/siisata.c | 6 +++---
sys/dev/marvell/gtethreg.h | 4 ++--
sys/dev/marvell/gtidmacreg.h | 4 ++--
sys/dev/marvell/gtreg.h | 6 +++---
sys/dev/mvme/if_ie_mvme.c | 6 +++---
sys/dev/pci/cxgb/cxgb_t3_hw.c | 4 ++--
sys/dev/pcmcia/if_malo_pcmcia.c | 8 ++++----
tests/ipf/h_common.sh | 4 ++--
19 files changed, 48 insertions(+), 48 deletions(-)
diffs (truncated from 430 to 300 lines):
diff -r 18ea9589491c -r 04c7ebb0df59 sbin/dkscan_bsdlabel/dkscan_bsdlabel.8
--- a/sbin/dkscan_bsdlabel/dkscan_bsdlabel.8 Wed Nov 10 16:57:39 2021 +0000
+++ b/sbin/dkscan_bsdlabel/dkscan_bsdlabel.8 Wed Nov 10 17:19:29 2021 +0000
@@ -1,4 +1,4 @@
-.\" $NetBSD: dkscan_bsdlabel.8,v 1.2 2008/04/30 13:10:52 martin Exp $
+.\" $NetBSD: dkscan_bsdlabel.8,v 1.3 2021/11/10 17:19:29 msaitoh Exp $
.\"
.\" Copyright (c) 2007 The NetBSD Foundation, Inc.
.\" All rights reserved.
@@ -41,7 +41,7 @@
.Nm
scans a disk for a BSD disklabel, which does not need to be the
label variant used on the architecture currently running, or even
-the same endianess.
+the same endianness.
.Pp
The following options are supported:
.Bl -tag -width device -compact
diff -r 18ea9589491c -r 04c7ebb0df59 sys/arch/mips/atheros/dev/ohci_arbus.c
--- a/sys/arch/mips/atheros/dev/ohci_arbus.c Wed Nov 10 16:57:39 2021 +0000
+++ b/sys/arch/mips/atheros/dev/ohci_arbus.c Wed Nov 10 17:19:29 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ohci_arbus.c,v 1.5 2021/08/07 16:18:59 thorpej Exp $ */
+/* $NetBSD: ohci_arbus.c,v 1.6 2021/11/10 17:19:29 msaitoh Exp $ */
/*-
* Copyright (c) 1998, 1999, 2000, 2002, 2003 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include "locators.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ohci_arbus.c,v 1.5 2021/08/07 16:18:59 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ohci_arbus.c,v 1.6 2021/11/10 17:19:29 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -107,7 +107,7 @@
if (ih == NULL)
panic("%s: couldn't establish interrupt", device_xname(self));
- /* we don't handle endianess in bus space */
+ /* we don't handle endianness in bus space */
sc->sc_endian = OHCI_LITTLE_ENDIAN;
int err = ohci_init(sc);
diff -r 18ea9589491c -r 04c7ebb0df59 sys/arch/mips/cavium/dev/octeon_xhci.c
--- a/sys/arch/mips/cavium/dev/octeon_xhci.c Wed Nov 10 16:57:39 2021 +0000
+++ b/sys/arch/mips/cavium/dev/octeon_xhci.c Wed Nov 10 17:19:29 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: octeon_xhci.c,v 1.6 2021/08/07 16:18:59 thorpej Exp $ */
+/* $NetBSD: octeon_xhci.c,v 1.7 2021/11/10 17:19:29 msaitoh Exp $ */
/* $OpenBSD: octxhci.c,v 1.4 2019/09/29 04:32:23 visa Exp $ */
/*
@@ -327,7 +327,7 @@
XCTL_WR_8(sc, XCTL_CTL, val);
(void)XCTL_RD_8(sc, XCTL_CTL);
- /* Fix endianess. */
+ /* Fix endianness. */
val = XCTL_RD_8(sc, XCTL_SHIM_CFG);
val &= ~XCTL_SHIM_CFG_CSR_BYTE_SWAP;
val &= ~XCTL_SHIM_CFG_DMA_BYTE_SWAP;
diff -r 18ea9589491c -r 04c7ebb0df59 sys/arch/mips/rmi/rmixl_ohci.c
--- a/sys/arch/mips/rmi/rmixl_ohci.c Wed Nov 10 16:57:39 2021 +0000
+++ b/sys/arch/mips/rmi/rmixl_ohci.c Wed Nov 10 17:19:29 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: rmixl_ohci.c,v 1.7 2021/08/07 16:18:59 thorpej Exp $ */
+/* $NetBSD: rmixl_ohci.c,v 1.8 2021/11/10 17:19:29 msaitoh Exp $ */
/*-
* Copyright (c) 1998, 1999, 2000, 2002, 2003 The NetBSD Foundation, Inc.
@@ -32,7 +32,7 @@
#include "locators.h"
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rmixl_ohci.c,v 1.7 2021/08/07 16:18:59 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rmixl_ohci.c,v 1.8 2021/11/10 17:19:29 msaitoh Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -115,7 +115,7 @@
device_xname(self));
}
- /* we handle endianess in bus space */
+ /* we handle endianness in bus space */
sc->sc_endian = OHCI_HOST_ENDIAN;
int err = ohci_init(sc);
diff -r 18ea9589491c -r 04c7ebb0df59 sys/arch/newsmips/apbus/if_snvar.h
--- a/sys/arch/newsmips/apbus/if_snvar.h Wed Nov 10 16:57:39 2021 +0000
+++ b/sys/arch/newsmips/apbus/if_snvar.h Wed Nov 10 17:19:29 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_snvar.h,v 1.14 2018/10/14 00:10:11 tsutsui Exp $ */
+/* $NetBSD: if_snvar.h,v 1.15 2021/11/10 17:19:29 msaitoh Exp $ */
/*
* Copyright (c) 1991 Algorithmics Ltd (http://www.algor.co.uk)
@@ -130,7 +130,7 @@
/*
* Accessing SONIC data structures and registers as 32 bit values
- * makes code endianess independent. The SONIC is however always in
+ * makes code endianness independent. The SONIC is however always in
* bigendian mode so it is necessary to ensure that data structures shared
* between the CPU and the SONIC are always in bigendian order.
*/
diff -r 18ea9589491c -r 04c7ebb0df59 sys/arch/sgimips/dev/crimereg.h
--- a/sys/arch/sgimips/dev/crimereg.h Wed Nov 10 16:57:39 2021 +0000
+++ b/sys/arch/sgimips/dev/crimereg.h Wed Nov 10 17:19:29 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: crimereg.h,v 1.10 2005/12/11 12:18:52 christos Exp $ */
+/* $NetBSD: crimereg.h,v 1.11 2021/11/10 17:19:29 msaitoh Exp $ */
/*
* Copyright (c) 2000 Soren S. Jorvang
@@ -55,7 +55,7 @@
#define CRIME_CONTROL_HARD_RESET 0x0800
#define CRIME_CONTROL_SOFT_RESET 0x0400
#define CRIME_CONTROL_DOG_ENABLE 0x0200
-#define CRIME_CONTROL_ENDIANESS 0x0100 /* assert for BE */
+#define CRIME_CONTROL_ENDIANNESS 0x0100 /* assert for BE */
#define CRIME_CONTROL_CQUEUE_HWM 0x000f
#define CRIME_CONTROL_CQUEUE_SHFT 0
#define CRIME_CONTROL_WBUF_HWM 0x00f0
diff -r 18ea9589491c -r 04c7ebb0df59 sys/dev/ic/ahcisata_core.c
--- a/sys/dev/ic/ahcisata_core.c Wed Nov 10 16:57:39 2021 +0000
+++ b/sys/dev/ic/ahcisata_core.c Wed Nov 10 17:19:29 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: ahcisata_core.c,v 1.103 2021/10/11 12:48:10 jmcneill Exp $ */
+/* $NetBSD: ahcisata_core.c,v 1.104 2021/11/10 17:19:30 msaitoh Exp $ */
/*
* Copyright (c) 2006 Manuel Bouyer.
@@ -26,7 +26,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.103 2021/10/11 12:48:10 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.104 2021/11/10 17:19:30 msaitoh Exp $");
#include <sys/types.h>
#include <sys/malloc.h>
@@ -1363,7 +1363,7 @@
AHCI_CMDH_SYNC(sc, achp, xfer->c_slot,
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
- /* ata(4) expects IDENTIFY data to be in host endianess */
+ /* ata(4) expects IDENTIFY data to be in host endianness */
if (ata_c->r_command == WDCC_IDENTIFY ||
ata_c->r_command == ATAPI_IDENTIFY_DEVICE) {
idwordbuf = xfer->c_databuf;
diff -r 18ea9589491c -r 04c7ebb0df59 sys/dev/ic/dm9000.c
--- a/sys/dev/ic/dm9000.c Wed Nov 10 16:57:39 2021 +0000
+++ b/sys/dev/ic/dm9000.c Wed Nov 10 17:19:29 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dm9000.c,v 1.30 2021/09/11 20:28:06 andvar Exp $ */
+/* $NetBSD: dm9000.c,v 1.31 2021/11/10 17:19:30 msaitoh Exp $ */
/*
* Copyright (c) 2009 Paul Fleischer
@@ -918,7 +918,7 @@
length++;
}
- /* Does shift direction depend on endianess? */
+ /* Does shift direction depend on endianness? */
left_over_buf = left_over_buf | (b << 8);
bus_space_write_2(sc->sc_iot, sc->sc_ioh,
@@ -956,7 +956,7 @@
to_write % 2));
left_over_count = 1;
/* XXX: Does this depend on
- * the endianess?
+ * the endianness?
*/
left_over_buf = *write_ptr;
diff -r 18ea9589491c -r 04c7ebb0df59 sys/dev/ic/i82596.c
--- a/sys/dev/ic/i82596.c Wed Nov 10 16:57:39 2021 +0000
+++ b/sys/dev/ic/i82596.c Wed Nov 10 17:19:29 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: i82596.c,v 1.44 2020/02/04 05:25:39 thorpej Exp $ */
+/* $NetBSD: i82596.c,v 1.45 2021/11/10 17:19:30 msaitoh Exp $ */
/*
* Copyright (c) 2003 Jochen Kunz.
@@ -43,7 +43,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: i82596.c,v 1.44 2020/02/04 05:25:39 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i82596.c,v 1.45 2021/11/10 17:19:30 msaitoh Exp $");
/* autoconfig and device stuff */
#include <sys/param.h>
@@ -120,7 +120,7 @@
* the chip.
*
* IEE_NEED_SWAP in sc->sc_flags has to be cleared on little endian hardware
- * and set on big endian hardware, when endianess conversion is not done
+ * and set on big endian hardware, when endianness conversion is not done
* by the bus attachment but done by i82596 chip itself.
* Usually you need to set IEE_NEED_SWAP on big endian machines
* where the hardware (the LE/~BE pin) is configured as BE mode.
diff -r 18ea9589491c -r 04c7ebb0df59 sys/dev/ic/mpt.h
--- a/sys/dev/ic/mpt.h Wed Nov 10 16:57:39 2021 +0000
+++ b/sys/dev/ic/mpt.h Wed Nov 10 17:19:29 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mpt.h,v 1.8 2014/09/27 16:14:16 jmcneill Exp $ */
+/* $NetBSD: mpt.h,v 1.9 2021/11/10 17:19:30 msaitoh Exp $ */
/*
* Copyright (c) 2000, 2001 by Greg Ansley
@@ -187,7 +187,7 @@
void mpt_print_config_request(void *);
void mpt_print_request(void *);
-/********************************** Endianess *********************************/
+/******************************** Endianness *********************************/
#define MPT_2_HOST64(ptr, tag) ptr->tag = le64toh(ptr->tag)
#define MPT_2_HOST32(ptr, tag) ptr->tag = le32toh(ptr->tag)
#define MPT_2_HOST16(ptr, tag) ptr->tag = le16toh(ptr->tag)
diff -r 18ea9589491c -r 04c7ebb0df59 sys/dev/ic/nvmeio.h
--- a/sys/dev/ic/nvmeio.h Wed Nov 10 16:57:39 2021 +0000
+++ b/sys/dev/ic/nvmeio.h Wed Nov 10 17:19:29 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: nvmeio.h,v 1.3 2018/04/19 21:50:08 christos Exp $ */
+/* $NetBSD: nvmeio.h,v 1.4 2021/11/10 17:19:30 msaitoh Exp $ */
/*-
* Copyright (C) 2012-2013 Intel Corporation
@@ -95,7 +95,7 @@
uint32_t timeout;
};
-/* Endianess conversion functions for NVMe structs */
+/* Endianness conversion functions for NVMe structs */
static __inline void
nvme_le128toh(uint64_t v[2])
{
diff -r 18ea9589491c -r 04c7ebb0df59 sys/dev/ic/siisata.c
--- a/sys/dev/ic/siisata.c Wed Nov 10 16:57:39 2021 +0000
+++ b/sys/dev/ic/siisata.c Wed Nov 10 17:19:29 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: siisata.c,v 1.49 2021/10/05 08:01:05 rin Exp $ */
+/* $NetBSD: siisata.c,v 1.50 2021/11/10 17:19:30 msaitoh Exp $ */
/* from ahcisata_core.c */
@@ -79,7 +79,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.49 2021/10/05 08:01:05 rin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.50 2021/11/10 17:19:30 msaitoh Exp $");
#include <sys/types.h>
#include <sys/param.h>
@@ -1142,7 +1142,7 @@
satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis);
}
- /* correct the endianess of IDENTIFY data */
+ /* correct the endianness of IDENTIFY data */
if (ata_c->r_command == WDCC_IDENTIFY ||
ata_c->r_command == ATAPI_IDENTIFY_DEVICE) {
idwordbuf = xfer->c_databuf;
diff -r 18ea9589491c -r 04c7ebb0df59 sys/dev/marvell/gtethreg.h
--- a/sys/dev/marvell/gtethreg.h Wed Nov 10 16:57:39 2021 +0000
+++ b/sys/dev/marvell/gtethreg.h Wed Nov 10 17:19:29 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: gtethreg.h,v 1.5 2010/04/28 13:51:56 kiyohara Exp $ */
+/* $NetBSD: gtethreg.h,v 1.6 2021/11/10 17:19:30 msaitoh Exp $ */
/*
* Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
@@ -54,7 +54,7 @@
* Descriptors used for both receive & transmit data. Note that the descriptor
* must start on a 4LW boundary. Since the GT accesses the descriptor as
* two 64-bit quantities, we must present them 32bit quantities in the right
- * order based on endianess.
+ * order based on endianness.
*/
struct gt_eth_desc {
diff -r 18ea9589491c -r 04c7ebb0df59 sys/dev/marvell/gtidmacreg.h
--- a/sys/dev/marvell/gtidmacreg.h Wed Nov 10 16:57:39 2021 +0000
+++ b/sys/dev/marvell/gtidmacreg.h Wed Nov 10 17:19:29 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: gtidmacreg.h,v 1.4 2017/01/07 14:32:32 kiyohara Exp $ */
+/* $NetBSD: gtidmacreg.h,v 1.5 2021/11/10 17:19:30 msaitoh Exp $ */
/*
* Copyright (c) 2008, 2009 KIYOHARA Takashi
* All rights reserved.
@@ -149,7 +149,7 @@
#define MVXORE_XEXCR_DBL_32B (2 << 8)
#define MVXORE_XEXCR_DBL_64B (3 << 8)
Home |
Main Index |
Thread Index |
Old Index