[src/trunk]: src/sys/dev/pci Whitespace fix. No functional change.

[msaitoh <msaitoh%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/1d274092f132
branches:  trunk
changeset: 1024099:1d274092f132
user:      msaitoh <msaitoh%NetBSD.org@localhost>
date:      Sun Oct 10 07:09:20 2021 +0000

description:
Whitespace fix. No functional change.

diffstat:

 sys/dev/pci/pcireg.h |  12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diffs (40 lines):

diff -r 8ec99a6622b1 -r 1d274092f132 sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h      Sat Oct 09 22:03:38 2021 +0000
+++ b/sys/dev/pci/pcireg.h      Sun Oct 10 07:09:20 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pcireg.h,v 1.158 2021/09/09 08:11:42 mrg Exp $ */
+/*     $NetBSD: pcireg.h,v 1.159 2021/10/10 07:09:20 msaitoh Exp $     */
 
 /*
  * Copyright (c) 1995, 1996, 1999, 2000
@@ -567,7 +567,7 @@
 #define        PCI_CAP_SUBVENDOR       0x0d
 #define        PCI_CAP_AGP8            0x0e
 #define        PCI_CAP_SECURE          0x0f
-#define        PCI_CAP_PCIEXPRESS      0x10
+#define        PCI_CAP_PCIEXPRESS      0x10
 #define        PCI_CAP_MSIX            0x11
 #define        PCI_CAP_SATA            0x12
 #define        PCI_CAP_PCIAF           0x13
@@ -1050,7 +1050,7 @@
 #define        PCIE_LCSR_NLW           __BITS(25, 20) /* Negotiated Link Width */
 #define        PCIE_LCSR_LINKTRAIN_ERR __BIT(10 + 16) /* Link Training Error */
 #define        PCIE_LCSR_LINKTRAIN     __BIT(11 + 16) /* Link Training */
-#define        PCIE_LCSR_SLOTCLKCFG    __BIT(12 + 16) /* Slot Clock Configuration */
+#define        PCIE_LCSR_SLOTCLKCFG    __BIT(12 + 16) /* Slot Clock Configuration */
 #define        PCIE_LCSR_DLACTIVE      __BIT(13 + 16) /* Data Link Layer Link Active*/
 #define        PCIE_LCSR_LINK_BW_MGMT  __BIT(14 + 16) /* Link BW Management Status */
 #define        PCIE_LCSR_LINK_AUTO_BW  __BIT(15 + 16) /* Link Autonomous BW Status */
@@ -1984,9 +1984,9 @@
 #define        PCI_TPH_REQ_CAP_DEVSPEC __BIT(2)   /* Device Specific Mode Supported */
 #define        PCI_TPH_REQ_CAP_XTPHREQ __BIT(8)    /* Extend TPH Requester Supported */
 #define        PCI_TPH_REQ_CAP_STTBLLOC __BITS(10, 9)  /* ST Table Location */
-#define        PCI_TPH_REQ_STTBLLOC_NONE       0       /* not present */
-#define        PCI_TPH_REQ_STTBLLOC_TPHREQ     1       /* in the TPHREQ cap */
-#define        PCI_TPH_REQ_STTBLLOC_MSIX       2       /* in the MSI-X table */
+#define        PCI_TPH_REQ_STTBLLOC_NONE       0        /* not present */
+#define        PCI_TPH_REQ_STTBLLOC_TPHREQ     1        /* in the TPHREQ cap */
+#define        PCI_TPH_REQ_STTBLLOC_MSIX       2        /* in the MSI-X table */
 #define        PCI_TPH_REQ_CAP_STTBLSIZ __BITS(26, 16) /* ST Table Size */
 #define        PCI_TPH_REQ_CTL 0x08    /* TPH Requester Control */
 #define        PCI_TPH_REQ_CTL_STSEL   __BITS(2, 0)    /* ST Mode Select */