[src/trunk]: src/sys/arch/arm/arm trailing whitespace/tab

[rin <rin%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/2d05c9ed1cf0
branches:  trunk
changeset: 1024003:2d05c9ed1cf0
user:      rin <rin%NetBSD.org@localhost>
date:      Thu Oct 07 09:57:27 2021 +0000

description:
trailing whitespace/tab

diffstat:

 sys/arch/arm/arm/cpufunc_asm_armv5.S |  8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diffs (36 lines):

diff -r 9150f20b1410 -r 2d05c9ed1cf0 sys/arch/arm/arm/cpufunc_asm_armv5.S
--- a/sys/arch/arm/arm/cpufunc_asm_armv5.S      Thu Oct 07 07:13:35 2021 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_armv5.S      Thu Oct 07 09:57:27 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_armv5.S,v 1.7 2014/03/30 01:15:03 matt Exp $       */
+/*     $NetBSD: cpufunc_asm_armv5.S,v 1.8 2021/10/07 09:57:27 rin Exp $        */
 
 /*
  * Copyright (c) 2002, 2005 ARM Limited
@@ -32,7 +32,7 @@
  * These routines can be used by any core that supports the set/index
  * operations.
  */
- 
+
 #include "assym.h"
 #include <machine/asm.h>
 #include <arm/locore.h>
@@ -130,7 +130,7 @@
        bpl     1b
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
        RET
-       
+
 ENTRY(armv5_dcache_wbinv_range)
        ldr     ip, .Larmv5_line_size
        cmp     r1, #0x4000
@@ -148,7 +148,7 @@
        bpl     1b
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
        RET
-       
+
 /*
  * Note, we must not invalidate everything.  If the range is too big we
  * must use wb-inv of the entire cache.