[src/trunk]: src/sys/arch Print the cache information in similar formats and ...

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/8b8853dbfe21
branches:  trunk
changeset: 1023690:8b8853dbfe21
user:      skrll <skrll%NetBSD.org@localhost>
date:      Thu Sep 23 06:34:00 2021 +0000

description:
Print the cache information in similar formats and arm and aarch64, e.g.

arm before
[   1.0000000] cpu0: 32KB/64B 2-way L1 PIPT Instruction cache
[   1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
[   1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache

arm after
[   1.0000000] cpu0: L1 32KB/64B 2-way (256 set) PIPT Instruction cache
[   1.0000000] cpu0: L1 32KB/64B 2-way (256 set) write-back-locking-C PIPT Data cache
[   1.0000000] cpu0: L2 2304KB/64B 16-way (2304 set) write-through PIPT Unified cache

aarch64 before
[   1.0000030] cpu1: L1 48KB/64B*256L*3W PIPT Instruction cache
[   1.0000030] cpu1: L1 32KB/64B*256L*2W PIPT Data cache
[   1.0000030] cpu1: L2 2048KB/64B*2048L*16W PIPT Unified cache

aarch64 after
[   1.0000030] cpu1: L1 48KB/64B 3-way (256 set) PIPT Instruction cache
[   1.0000030] cpu1: L1 32KB/64B 2-way (256 set) PIPT Data cache
[   1.0000030] cpu1: L2 2048KB/64B 16-way (2048 set) PIPT Unified cache

diffstat:

 sys/arch/aarch64/aarch64/cpufunc.c |   8 ++++----
 sys/arch/arm/arm32/cpu.c           |  22 ++++++++++++++--------
 2 files changed, 18 insertions(+), 12 deletions(-)

diffs (86 lines):

diff -r 005ba1e2cfd3 -r 8b8853dbfe21 sys/arch/aarch64/aarch64/cpufunc.c
--- a/sys/arch/aarch64/aarch64/cpufunc.c        Wed Sep 22 17:37:31 2021 +0000
+++ b/sys/arch/aarch64/aarch64/cpufunc.c        Thu Sep 23 06:34:00 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc.c,v 1.27 2021/01/11 17:12:13 skrll Exp $       */
+/*     $NetBSD: cpufunc.c,v 1.28 2021/09/23 06:34:00 skrll Exp $       */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -30,7 +30,7 @@
 #include "opt_multiprocessor.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.27 2021/01/11 17:12:13 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.28 2021/09/23 06:34:00 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/types.h>
@@ -295,12 +295,12 @@
                }
 
                aprint_verbose_dev(self,
-                   "L%d %uKB/%uB*%uL*%uW %s %s cache\n",
+                   "L%d %uKB/%uB %u-way (%u set) %s %s cache\n",
                    level + 1,
                    cunit->cache_size / 1024,
                    cunit->cache_line_size,
+                   cunit->cache_ways,
                    cunit->cache_sets,
-                   cunit->cache_ways,
                    cachetype, cacheable);
 
                if (cinfo[level].cacheable != CACHE_CACHEABLE_IDCACHE)
diff -r 005ba1e2cfd3 -r 8b8853dbfe21 sys/arch/arm/arm32/cpu.c
--- a/sys/arch/arm/arm32/cpu.c  Wed Sep 22 17:37:31 2021 +0000
+++ b/sys/arch/arm/arm32/cpu.c  Thu Sep 23 06:34:00 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpu.c,v 1.148 2021/07/06 08:34:28 skrll Exp $  */
+/*     $NetBSD: cpu.c,v 1.149 2021/09/23 06:34:00 skrll Exp $  */
 
 /*
  * Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
 #include "opt_multiprocessor.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.148 2021/07/06 08:34:28 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.149 2021/09/23 06:34:00 skrll Exp $");
 
 #include <sys/param.h>
 
@@ -608,22 +608,28 @@
 print_cache_info(device_t dv, struct arm_cache_info *info, u_int level)
 {
        if (info->cache_unified) {
-               aprint_normal_dev(dv, "%dKB/%dB %d-way %s L%u %cI%cT Unified cache\n",
+               aprint_normal_dev(dv, "L%u %dKB/%dB %d-way (%u set) %s %cI%cT Unified cache\n",
+                   level + 1,
                    info->dcache_size / 1024,
                    info->dcache_line_size, info->dcache_ways,
-                   wtnames[info->cache_type], level + 1,
+                   info->dcache_sets,
+                   wtnames[info->cache_type],
                    info->dcache_type & CACHE_TYPE_PIxx ? 'P' : 'V',
                    info->dcache_type & CACHE_TYPE_xxPT ? 'P' : 'V');
        } else {
-               aprint_normal_dev(dv, "%dKB/%dB %d-way L%u %cI%cT Instruction cache\n",
+               aprint_normal_dev(dv, "L%u %dKB/%dB %d-way (%u set) %cI%cT Instruction cache\n",
+                   level + 1,
                    info->icache_size / 1024,
-                   info->icache_line_size, info->icache_ways, level + 1,
+                   info->icache_line_size, info->icache_ways,
+                   info->icache_sets,
                    info->icache_type & CACHE_TYPE_PIxx ? 'P' : 'V',
                    info->icache_type & CACHE_TYPE_xxPT ? 'P' : 'V');
-               aprint_normal_dev(dv, "%dKB/%dB %d-way %s L%u %cI%cT Data cache\n",
+               aprint_normal_dev(dv, "L%u %dKB/%dB %d-way (%u set) %s %cI%cT Data cache\n",
+                   level + 1,
                    info->dcache_size / 1024,
                    info->dcache_line_size, info->dcache_ways,
-                   wtnames[info->cache_type], level + 1,
+                   info->dcache_sets,
+                   wtnames[info->cache_type],
                    info->dcache_type & CACHE_TYPE_PIxx ? 'P' : 'V',
                    info->dcache_type & CACHE_TYPE_xxPT ? 'P' : 'V');
        }