[src/trunk]: src/sys/arch/aarch64/aarch64 In pmap_icache_sync_range change

[skrll <skrll%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/6ec2e10cbf91
branches:  trunk
changeset: 1023465:6ec2e10cbf91
user:      skrll <skrll%NetBSD.org@localhost>
date:      Thu Sep 09 08:12:27 2021 +0000

description:
In pmap_icache_sync_range change

for (...) {
        ...
        if (condition) {
                // do stuff
        }
}

to

for (...) {
        ...
        if (!conditional)
                continue;
        // do stuff
}

to save on indentation. Same code (modulo register usage) before and
after.

diffstat:

 sys/arch/aarch64/aarch64/pmap.c |  39 ++++++++++++++++++++-------------------
 1 files changed, 20 insertions(+), 19 deletions(-)

diffs (60 lines):

diff -r 7df9db210b15 -r 6ec2e10cbf91 sys/arch/aarch64/aarch64/pmap.c
--- a/sys/arch/aarch64/aarch64/pmap.c   Thu Sep 09 08:11:42 2021 +0000
+++ b/sys/arch/aarch64/aarch64/pmap.c   Thu Sep 09 08:12:27 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.c,v 1.109 2021/09/09 08:09:44 skrll Exp $ */
+/*     $NetBSD: pmap.c,v 1.110 2021/09/09 08:12:27 skrll Exp $ */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.109 2021/09/09 08:09:44 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.110 2021/09/09 08:12:27 skrll Exp $");
 
 #include "opt_arm_debug.h"
 #include "opt_ddb.h"
@@ -967,23 +967,24 @@
                }
 
                pte = *ptep;
-               if (lxpde_valid(pte)) {
-                       vaddr_t eob = (va + blocksize) & ~(blocksize - 1);
-                       vsize_t len = ulmin(eva, eob) - va;
-
-                       if (l3pte_readable(pte)) {
-                               cpu_icache_sync_range(va, len);
-                       } else {
-                               /*
-                                * change to accessible temporally
-                                * to do cpu_icache_sync_range()
-                                */
-                               atomic_swap_64(ptep, pte | LX_BLKPAG_AF);
-                               AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, true);
-                               cpu_icache_sync_range(va, len);
-                               atomic_swap_64(ptep, pte);
-                               AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, true);
-                       }
+               if (!lxpde_valid(pte))
+                       continue;
+
+               vaddr_t eob = (va + blocksize) & ~(blocksize - 1);
+               vsize_t len = ulmin(eva, eob) - va;
+
+               if (l3pte_readable(pte)) {
+                       cpu_icache_sync_range(va, len);
+               } else {
+                       /*
+                        * change to accessible temporally
+                        * to do cpu_icache_sync_range()
+                        */
+                       atomic_swap_64(ptep, pte | LX_BLKPAG_AF);
+                       AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, true);
+                       cpu_icache_sync_range(va, len);
+                       atomic_swap_64(ptep, pte);
+                       AARCH64_TLBI_BY_ASID_VA(pm->pm_asid, va, true);
                }
        }