[src/trunk]: src/sys/dev/pci add some bits in the pci Link Capabilities Regis...

[mrg <mrg%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/cbb00d7434b5
branches:  trunk
changeset: 1023462:cbb00d7434b5
user:      mrg <mrg%NetBSD.org@localhost>
date:      Thu Sep 09 02:12:48 2021 +0000

description:
add some bits in the pci Link Capabilities Register, and also the similar
set in the Link Capabilities 2 Register.

diffstat:

 sys/dev/pci/pcireg.h |  14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletions(-)

diffs (35 lines):

diff -r add79fe0243e -r cbb00d7434b5 sys/dev/pci/pcireg.h
--- a/sys/dev/pci/pcireg.h      Thu Sep 09 01:14:04 2021 +0000
+++ b/sys/dev/pci/pcireg.h      Thu Sep 09 02:12:48 2021 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pcireg.h,v 1.156 2021/08/17 22:00:32 andvar Exp $      */
+/*     $NetBSD: pcireg.h,v 1.157 2021/09/09 02:12:48 mrg Exp $ */
 
 /*
  * Copyright (c) 1995, 1996, 1999, 2000
@@ -1017,6 +1017,12 @@
 #define PCIE_DCSR_EMGPWRREDD   __BIT(6 + 16)  /* Emg. Pwr. Reduct. Detected */
 #define PCIE_LCAP      0x0c    /* Link Capabilities Register */
 #define PCIE_LCAP_MAX_SPEED    __BITS(3, 0)   /* Max Link Speed */
+#define  PCIE_LCAP_MAX_SPEED_2 __BIT(0)       /* 2.5GT/s */
+#define  PCIE_LCAP_MAX_SPEED_5 __BIT(1)       /* 5GT/s */
+#define  PCIE_LCAP_MAX_SPEED_8 __BIT(3)       /* 8GT/s */
+#define  PCIE_LCAP_MAX_SPEED_16        __BIT(4)       /* 16GT/s */
+#define  PCIE_LCAP_MAX_SPEED_32        __BIT(5)       /* 32GT/s */
+#define  PCIE_LCAP_MAX_SPEED_64        __BIT(6)       /* 64GT/s */
 #define PCIE_LCAP_MAX_WIDTH    __BITS(9, 4)   /* Maximum Link Width */
 #define PCIE_LCAP_ASPM         __BITS(11, 10) /* Active State Link PM Supp. */
 #define PCIE_LCAP_L0S_EXIT     __BITS(14, 12) /* L0s Exit Latency */
@@ -1136,6 +1142,12 @@
 #define PCIE_DCSR2_EETLP       __BIT(15)      /* End-End TLP Prefix Blcking */
 #define PCIE_LCAP2     0x2c    /* Link Capabilities 2 Register */
 #define PCIE_LCAP2_SUP_LNKSV   __BITS(7, 1)   /* Supported Link Speeds Vect */
+#define  PCIE_LCAP2_SUP_LNKS2  __BIT(1)       /* Supported Speed 2.5GT/ */
+#define  PCIE_LCAP2_SUP_LNKS5  __BIT(2)       /* Supported Speed 5GT/ */
+#define  PCIE_LCAP2_SUP_LNKS8  __BIT(3)       /* Supported Speed 8GT/ */
+#define  PCIE_LCAP2_SUP_LNKS16 __BIT(4)       /* Supported Speed 16GT/ */
+#define  PCIE_LCAP2_SUP_LNKS32 __BIT(5)       /* Supported Speed 32GT/ */
+#define  PCIE_LCAP2_SUP_LNKS64 __BIT(6)       /* Supported Speed 64GT/ */
 #define PCIE_LCAP2_CROSSLNK    __BIT(8)       /* Crosslink Supported */
 #define PCIE_LCAP2_LOWSKPOS_GENSUPPSV __BITS(15, 9)
                                  /* Lower SKP OS Generation Supp. Spd. Vect */