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[src/trunk]: src/sys/arch Add support for Amlogic S922X(meson-g12b) SoCs



details:   https://anonhg.NetBSD.org/src/rev/b2193a1bf0bc
branches:  trunk
changeset: 1017583:b2193a1bf0bc
user:      ryo <ryo%NetBSD.org@localhost>
date:      Fri Jan 01 07:21:58 2021 +0000

description:
Add support for Amlogic S922X(meson-g12b) SoCs

diffstat:

 sys/arch/arm/amlogic/files.meson            |    38 +-
 sys/arch/arm/amlogic/meson_clk.h            |    30 +-
 sys/arch/arm/amlogic/meson_clk_pll.c        |    91 +-
 sys/arch/arm/amlogic/meson_pinctrl.c        |    34 +-
 sys/arch/arm/amlogic/meson_pinctrl.h        |    12 +-
 sys/arch/arm/amlogic/meson_pwm.c            |   391 ++++++
 sys/arch/arm/amlogic/meson_thermal.c        |   246 ++++
 sys/arch/arm/amlogic/meson_usbctrl.c        |   299 +++++
 sys/arch/arm/amlogic/mesong12_aoclkc.c      |   135 ++
 sys/arch/arm/amlogic/mesong12_aoclkc.h      |    71 +
 sys/arch/arm/amlogic/mesong12_clkc.c        |  1534 +++++++++++++++++++++++++++
 sys/arch/arm/amlogic/mesong12_clkc.h        |   334 +++++
 sys/arch/arm/amlogic/mesong12_usb2phy.c     |   340 +++++
 sys/arch/arm/amlogic/mesong12_usb3pciephy.c |   356 ++++++
 sys/arch/arm/amlogic/mesong12a_pinctrl.c    |   676 +++++++++++
 sys/arch/evbarm/conf/GENERIC64              |    11 +-
 16 files changed, 4581 insertions(+), 17 deletions(-)

diffs (truncated from 4833 to 300 lines):

diff -r 12bc74f02c2f -r b2193a1bf0bc sys/arch/arm/amlogic/files.meson
--- a/sys/arch/arm/amlogic/files.meson  Fri Jan 01 07:18:23 2021 +0000
+++ b/sys/arch/arm/amlogic/files.meson  Fri Jan 01 07:21:58 2021 +0000
@@ -1,4 +1,4 @@
-#      $NetBSD: files.meson,v 1.10 2019/08/14 15:08:53 skrll Exp $
+#      $NetBSD: files.meson,v 1.11 2021/01/01 07:21:58 ryo Exp $
 #
 # Configuration info for Amlogic Meson family SoCs
 #
@@ -32,6 +32,16 @@
 attach gxbbaoclkc at fdt with mesongxbb_aoclkc
 file   arch/arm/amlogic/mesongxbb_aoclkc.c     mesongxbb_aoclkc
 
+# Meson G12[AB] clock controller
+device g12clkc: meson_clk
+attach g12clkc at fdt with mesong12_clkc
+file   arch/arm/amlogic/mesong12_clkc.c        mesong12_clkc
+
+# Meson G12[AB] AO clock controller
+device g12aoclkc: meson_clk
+attach g12aoclkc at fdt with mesong12_aoclkc
+file   arch/arm/amlogic/mesong12_aoclkc.c      mesong12_aoclkc
+
 # Meson reset controller
 device mesonresets
 attach mesonresets at fdt with meson_resets
@@ -52,6 +62,7 @@
 attach mesonpinctrl at fdt with meson_pinctrl
 file   arch/arm/amlogic/meson_pinctrl.c        meson_pinctrl
 file   arch/arm/amlogic/meson8b_pinctrl.c      meson_pinctrl & soc_meson8b
+file   arch/arm/amlogic/mesong12a_pinctrl.c    meson_pinctrl & soc_mesong12
 file   arch/arm/amlogic/mesongxbb_pinctrl.c    meson_pinctrl & soc_mesongxbb
 file   arch/arm/amlogic/mesongxl_pinctrl.c     meson_pinctrl & soc_mesongxl
 
@@ -85,6 +96,21 @@
 attach mesongxlu3phy at fdt with mesongxl_usb3phy
 file   arch/arm/amlogic/mesongxl_usb3phy.c     mesongxl_usb3phy
 
+# Meson G12 USB2 PHY
+device mesong12u2phy
+attach mesong12u2phy at fdt with mesong12_usb2phy
+file   arch/arm/amlogic/mesong12_usb2phy.c     mesong12_usb2phy
+
+# Meson G12 USB3/PCIE PHY
+device mesong12u3pphy
+attach mesong12u3pphy at fdt with mesong12_usb3pciephy
+file   arch/arm/amlogic/mesong12_usb3pciephy.c mesong12_usb3pciephy
+
+# Meson G12 USB
+device mesonusbctrl
+attach mesonusbctrl at fdt with meson_usbctrl
+file   arch/arm/amlogic/meson_usbctrl.c        meson_usbctrl
+
 # RTC
 device mesonrtc
 attach mesonrtc at fdt with meson_rtc
@@ -119,6 +145,16 @@
 attach meson6timer at fdt with meson6_timer
 file   arch/arm/amlogic/meson6_timer.c         meson6_timer
 
+# Meson PWM
+device mesonpwm
+attach mesonpwm at fdt with meson_pwm
+file   arch/arm/amlogic/meson_pwm.c            meson_pwm
+
+# Meson Thermal
+device mesonthermal
+attach mesonthermal at fdt with meson_thermal
+file   arch/arm/amlogic/meson_thermal.c        meson_thermal
+
 # SOC parameters
 defflag        opt_soc.h                       SOC_MESON
 defflag        opt_soc.h                       SOC_MESON8B: SOC_MESON
diff -r 12bc74f02c2f -r b2193a1bf0bc sys/arch/arm/amlogic/meson_clk.h
--- a/sys/arch/arm/amlogic/meson_clk.h  Fri Jan 01 07:18:23 2021 +0000
+++ b/sys/arch/arm/amlogic/meson_clk.h  Fri Jan 01 07:21:58 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: meson_clk.h,v 1.3 2019/02/25 19:30:17 jmcneill Exp $ */
+/* $NetBSD: meson_clk.h,v 1.4 2021/01/01 07:21:58 ryo Exp $ */
 
 /*-
  * Copyright (c) 2017-2019 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -196,6 +196,22 @@
 const char *meson_clk_mux_get_parent(struct meson_clk_softc *,
                               struct meson_clk_clk *);
 
+#define        MESON_CLK_MUX_RATE(_id, _name, _parents, _reg, _sel,            \
+                          _getratefn, _setratefn, _flags)              \
+       [_id] = {                                                       \
+               .type = MESON_CLK_MUX,                                  \
+               .base.name = (_name),                                   \
+               .base.flags = 0,                                        \
+               .u.mux.parents = (_parents),                            \
+               .u.mux.nparents = __arraycount(_parents),               \
+               .u.mux.reg = (_reg),                                    \
+               .u.mux.sel = (_sel),                                    \
+               .u.mux.flags = (_flags),                                \
+               .get_rate = _getratefn,                                 \
+               .set_rate = _setratefn,                                 \
+               .get_parent = meson_clk_mux_get_parent,                 \
+       }
+
 #define        MESON_CLK_MUX(_id, _name, _parents, _reg, _sel, _flags)         \
        [_id] = {                                                       \
                .type = MESON_CLK_MUX,                                  \
@@ -235,8 +251,13 @@
 
 u_int  meson_clk_pll_get_rate(struct meson_clk_softc *,
                               struct meson_clk_clk *);
+int    meson_clk_pll_set_rate(struct meson_clk_softc *,
+                              struct meson_clk_clk *, u_int new_rate);
 const char *meson_clk_pll_get_parent(struct meson_clk_softc *,
                                     struct meson_clk_clk *);
+int    meson_clk_pll_wait_lock(struct meson_clk_softc *sc,
+                               struct meson_clk_pll *pll);
+
 
 #define        MESON_CLK_PLL_RATE(_id, _name, _parent, _enable, _m, _n, _frac, _l,     \
                      _reset, _setratefn, _flags)                       \
@@ -368,5 +389,12 @@
 #define        CLK_UNLOCK      meson_clk_unlock
 #define        CLK_READ        meson_clk_read
 #define        CLK_WRITE       meson_clk_write
+#define CLK_WRITE_BITS(sc, reg, mask, val)                     \
+       do {                                                    \
+               uint32_t _cwb_tmp_ = CLK_READ((sc), (reg));     \
+               _cwb_tmp_ &= ~(mask);                           \
+               _cwb_tmp_ |= __SHIFTIN((val), (mask));          \
+               CLK_WRITE((sc), (reg), _cwb_tmp_);              \
+       } while (0 /*CONSTCOND*/)
 
 #endif /* _ARM_MESON_CLK_H */
diff -r 12bc74f02c2f -r b2193a1bf0bc sys/arch/arm/amlogic/meson_clk_pll.c
--- a/sys/arch/arm/amlogic/meson_clk_pll.c      Fri Jan 01 07:18:23 2021 +0000
+++ b/sys/arch/arm/amlogic/meson_clk_pll.c      Fri Jan 01 07:21:58 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: meson_clk_pll.c,v 1.2 2019/02/25 19:30:17 jmcneill Exp $ */
+/* $NetBSD: meson_clk_pll.c,v 1.3 2021/01/01 07:21:58 ryo Exp $ */
 
 /*-
  * Copyright (c) 2019 Jared McNeill <jmcneill%invisible.ca@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: meson_clk_pll.c,v 1.2 2019/02/25 19:30:17 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: meson_clk_pll.c,v 1.3 2021/01/01 07:21:58 ryo Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -83,6 +83,93 @@
        return (u_int)howmany(rate, n);
 }
 
+/* the lock must have been acquired with CLK_LOCK() */
+int
+meson_clk_pll_wait_lock(struct meson_clk_softc *sc, struct meson_clk_pll *pll)
+{
+       int i;
+       for (i = 24000000; i > 0; i--) {
+               if ((CLK_READ(sc, pll->l.reg) & pll->l.mask) != 0)
+                       return 0;
+       }
+       return ETIMEDOUT;
+}
+
+int
+meson_clk_pll_set_rate(struct meson_clk_softc *sc, struct meson_clk_clk *clk,
+    u_int new_rate)
+{
+       struct meson_clk_pll *pll = &clk->u.pll;
+       struct clk *clkp, *clkp_parent;
+       uint64_t parent_rate, tmp;
+       uint32_t n, m, m_max, frac, frac_max;
+       int error;
+
+       KASSERT(clk->type == MESON_CLK_PLL);
+
+       clkp = &clk->base;
+       clkp_parent = clk_get_parent(clkp);
+       if (clkp_parent == NULL)
+               return ENXIO;
+
+       if ((pll->flags & MESON_CLK_DIV_SET_RATE_PARENT) != 0)
+               return clk_set_rate(clkp_parent, new_rate);
+
+       parent_rate = clk_get_rate(clkp_parent);
+       if (parent_rate == 0) {
+               error = (new_rate == 0) ? 0 : ERANGE;
+               return error;
+       }
+
+       if (parent_rate > new_rate) {
+               n = parent_rate / new_rate;
+               parent_rate /= n;
+       } else {
+               n = 1;
+       }
+
+#define DIV_ROUND_OFF(x, y) (((x) + (y) / 2) / (y))
+       m_max = __SHIFTOUT(pll->m.mask, pll->m.mask);
+       frac_max = __SHIFTOUT(pll->frac.mask, pll->frac.mask);
+       tmp = DIV_ROUND_OFF(new_rate * (frac_max + 1), parent_rate);
+       m = tmp / (frac_max + 1);
+       frac = tmp & frac_max;
+
+       if (m > m_max)
+               return ERANGE;
+
+       CLK_LOCK(sc);
+
+       /* reset */
+       CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 1);
+       CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 0);
+       error = meson_clk_pll_wait_lock(sc, pll);
+       if (error != 0)
+               goto failure;
+
+       /* disable */
+       CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 1);
+       CLK_WRITE_BITS(sc, pll->enable.reg, pll->enable.mask, 0);
+
+       /* write new M, N, and FRAC */
+       CLK_WRITE_BITS(sc, pll->m.reg, pll->m.mask, m);
+       CLK_WRITE_BITS(sc, pll->n.reg, pll->n.mask, n);
+       if (pll->frac.mask) {
+               CLK_WRITE_BITS(sc, pll->frac.reg, pll->frac.mask, frac);
+       }
+
+       /* enable */
+       CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 1);
+       CLK_WRITE_BITS(sc, pll->enable.reg, pll->enable.mask, 1);
+       DELAY(1000);
+       CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 0);
+       error = meson_clk_pll_wait_lock(sc, pll);
+ failure:
+       CLK_UNLOCK(sc);
+
+       return error;
+}
+
 const char *
 meson_clk_pll_get_parent(struct meson_clk_softc *sc,
     struct meson_clk_clk *clk)
diff -r 12bc74f02c2f -r b2193a1bf0bc sys/arch/arm/amlogic/meson_pinctrl.c
--- a/sys/arch/arm/amlogic/meson_pinctrl.c      Fri Jan 01 07:18:23 2021 +0000
+++ b/sys/arch/arm/amlogic/meson_pinctrl.c      Fri Jan 01 07:21:58 2021 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: meson_pinctrl.c,v 1.6 2019/10/01 23:32:52 jmcneill Exp $ */
+/* $NetBSD: meson_pinctrl.c,v 1.7 2021/01/01 07:21:58 ryo Exp $ */
 
 /*-
  * Copyright (c) 2019 Jared D. McNeill <jmcneill%invisible.ca@localhost>
@@ -29,7 +29,7 @@
 #include "opt_soc.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: meson_pinctrl.c,v 1.6 2019/10/01 23:32:52 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: meson_pinctrl.c,v 1.7 2021/01/01 07:21:58 ryo Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -84,6 +84,10 @@
        { "amlogic,meson-gxl-aobus-pinctrl",    (uintptr_t)&mesongxl_aobus_pinctrl_config },
        { "amlogic,meson-gxl-periphs-pinctrl",  (uintptr_t)&mesongxl_periphs_pinctrl_config },
 #endif
+#ifdef SOC_MESONG12
+       { "amlogic,meson-g12a-aobus-pinctrl",   (uintptr_t)&mesong12a_aobus_pinctrl_config },
+       { "amlogic,meson-g12a-periphs-pinctrl", (uintptr_t)&mesong12a_periphs_pinctrl_config },
+#endif
        { NULL, 0 }
 };
 
@@ -129,10 +133,16 @@
        uint32_t val;
 
        val = MUX_READ(sc, group->reg);
-       if (enable)
-               val |= __BIT(group->bit);
-       else
-               val &= ~__BIT(group->bit);
+       if (group->mask == 0) {
+               if (enable)
+                       val |= __BIT(group->bit);
+               else
+                       val &= ~__BIT(group->bit);
+       } else {
+               val &= ~group->mask;
+               if (enable)
+                       val |= __SHIFTIN(group->func, group->mask);
+       }
        MUX_WRITE(sc, group->reg, val);
 }
 
@@ -432,17 +442,19 @@
                                aprint_error(": couldn't map mux registers\n");
                                return ENXIO;
                        }
-                       if (fdtbus_get_reg_byname(child, "pull", &addr, &size) != 0 ||
-                           bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh_pull) != 0) {



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